SVE Instruction List by Dougall Johnson
LSR (vectors): Logical shift right by vector (predicated)
LSR Zdn.S, Pg/M, Zdn.S, Zm.S (SVE (SME
svuint32_t svlsr[_u32]_m(svbool_t pg, svuint32_t op1, svuint32_t op2)
128-bit SVE
For each 32-bit unsigned integer set (3) to (1) >> (2). If (2) is greater than 31 or less than 0, the result is 0.
256-bit SVE
For each 32-bit unsigned integer set (3) to (1) >> (2). If (2) is greater than 31 or less than 0, the result is 0.
512-bit SVE
For each 32-bit unsigned integer set (3) to (1) >> (2). If (2) is greater than 31 or less than 0, the result is 0.
Larger sizes
1024-bit SVE
For each 32-bit unsigned integer set (3) to (1) >> (2). If (2) is greater than 31 or less than 0, the result is 0.
2048-bit SVE
For each 32-bit unsigned integer set (3) to (1) >> (2). If (2) is greater than 31 or less than 0, the result is 0.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.