SVE Instruction List by Dougall Johnson
LSR (immediate, unpredicated): Logical shift right by immediate (unpredicated)
LSR Zd.S, Zn.S, #const (SVE (SME
svuint32_t svlsr[_n_u32]_x(svbool_t pg, svuint32_t op1, uint32_t op2)
svuint32_t svlsr_wide[_n_u32]_x(svbool_t pg, svuint32_t op1, uint64_t op2)
128-bit SVE

For each 32-bit unsigned integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 32.
256-bit SVE

For each 32-bit unsigned integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 32.
512-bit SVE

For each 32-bit unsigned integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 32.
Larger sizes
1024-bit SVE

For each 32-bit unsigned integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 32.
2048-bit SVE

For each 32-bit unsigned integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 32.
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.