SVE Instruction List by Dougall Johnson
LSR (immediate, unpredicated): Logical shift right by immediate (unpredicated)
LSR Zd.D, Zn.D, #const (SVE (SME
svuint64_t svlsr[_n_u64]_x(svbool_t pg, svuint64_t op1, uint64_t op2)
128-bit SVE

For each 64-bit unsigned integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 64.
256-bit SVE

For each 64-bit unsigned integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 64.
512-bit SVE

For each 64-bit unsigned integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 64.
Larger sizes
1024-bit SVE

For each 64-bit unsigned integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 64.
2048-bit SVE

For each 64-bit unsigned integer set (2) to (1) >> const. The shift amount is limited to 1 ≤ const ≤ 64.
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.