SVE Instruction List by Dougall Johnson
LSRR: Reversed logical shift right by vector (predicated)
LSRR Zdn.D, Pg/M, Zdn.D, Zm.D (SVE (SME
128-bit SVE
For each 64-bit unsigned integer set (3) to (2) >> (1). If (1) is greater than 63 or less than 0, the result is 0.
256-bit SVE
For each 64-bit unsigned integer set (3) to (2) >> (1). If (1) is greater than 63 or less than 0, the result is 0.
512-bit SVE
For each 64-bit unsigned integer set (3) to (2) >> (1). If (1) is greater than 63 or less than 0, the result is 0.
Larger sizes
1024-bit SVE
For each 64-bit unsigned integer set (3) to (2) >> (1). If (1) is greater than 63 or less than 0, the result is 0.
2048-bit SVE
For each 64-bit unsigned integer set (3) to (2) >> (1). If (1) is greater than 63 or less than 0, the result is 0.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.