SVE Instruction List by Dougall Johnson
PEXT (predicate pair): Set pair of predicates from predicate-as-counter
PEXT { Pd1.D, Pd2.D }, PNn[imm] (SVE2.1 (SME2+S
128-bit SVE
Decode (1) from predicate-as-counter representation to a quadruple-length predicate, select the half indicated by imm, and copy the bits corresponding to 64-bit elements to two consecutive destination registers (2), zeroing all other bits.
256-bit SVE
Decode (1) from predicate-as-counter representation to a quadruple-length predicate, select the half indicated by imm, and copy the bits corresponding to 64-bit elements to two consecutive destination registers (2), zeroing all other bits.
512-bit SVE
Decode (1) from predicate-as-counter representation to a quadruple-length predicate, select the half indicated by imm, and copy the bits corresponding to 64-bit elements to two consecutive destination registers (2), zeroing all other bits.
Larger sizes
1024-bit SVE
Decode (1) from predicate-as-counter representation to a quadruple-length predicate, select the half indicated by imm, and copy the bits corresponding to 64-bit elements to two consecutive destination registers (2), zeroing all other bits.
2048-bit SVE
Decode (1) from predicate-as-counter representation to a quadruple-length predicate, select the half indicated by imm, and copy the bits corresponding to 64-bit elements to two consecutive destination registers (2), zeroing all other bits.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.