SVE Instruction List by Dougall Johnson
PEXT (predicate pair): Set pair of predicates from predicate-as-counter
PEXT { Pd1.B, Pd2.B }, PNn[imm] (SVE2.1 (SME2+S
128-bit SVE
Decode (1) from predicate-as-counter representation to a quadruple-length predicate, and copy the half indicated by imm to two consecutive destination registers (2).
256-bit SVE
Decode (1) from predicate-as-counter representation to a quadruple-length predicate, and copy the half indicated by imm to two consecutive destination registers (2).
512-bit SVE
Decode (1) from predicate-as-counter representation to a quadruple-length predicate, and copy the half indicated by imm to two consecutive destination registers (2).
Larger sizes
1024-bit SVE
Decode (1) from predicate-as-counter representation to a quadruple-length predicate, and copy the half indicated by imm to two consecutive destination registers (2).
2048-bit SVE
Decode (1) from predicate-as-counter representation to a quadruple-length predicate, and copy the half indicated by imm to two consecutive destination registers (2).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.