SVE Instruction List by Dougall Johnson
PMULL: Multi-vector polynomial multiply long
PMULL { Zd1.Q-Zd2.Q }, Zn.D, Zm.D (SVE-AES2+NS (SSVE-AES+AES2
128-bit SVE
Interpreting each 64-bit element from (1) and (2) as a ℤ2 polynomial, set each double-width element of (3) to the product of the corresponding even pair, and each element of (4) to the product of the corresponding odd pair. This can also be described as a carryless multiplication, or a multiplication using exclusive-or instead of addition.
256-bit SVE
Interpreting each 64-bit element from (1) and (2) as a ℤ2 polynomial, set each double-width element of (3) to the product of the corresponding even pair, and each element of (4) to the product of the corresponding odd pair. This can also be described as a carryless multiplication, or a multiplication using exclusive-or instead of addition.
512-bit SVE
Interpreting each 64-bit element from (1) and (2) as a ℤ2 polynomial, set each double-width element of (3) to the product of the corresponding even pair, and each element of (4) to the product of the corresponding odd pair. This can also be described as a carryless multiplication, or a multiplication using exclusive-or instead of addition.
Larger sizes
1024-bit SVE
Interpreting each 64-bit element from (1) and (2) as a ℤ2 polynomial, set each double-width element of (3) to the product of the corresponding even pair, and each element of (4) to the product of the corresponding odd pair. This can also be described as a carryless multiplication, or a multiplication using exclusive-or instead of addition.
2048-bit SVE
Interpreting each 64-bit element from (1) and (2) as a ℤ2 polynomial, set each double-width element of (3) to the product of the corresponding even pair, and each element of (4) to the product of the corresponding odd pair. This can also be described as a carryless multiplication, or a multiplication using exclusive-or instead of addition.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.