SVE Instruction List by Dougall Johnson
SMAXQV: Signed maximum reduction of quadword vector segments
SMAXQV Vd.8H, Pg, Zn.H (SVE2.1 (SME2.1
128-bit SVE
Take the minimum across corresponding active signed 16-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, interpret it as −0x8000.
256-bit SVE
Take the minimum across corresponding active signed 16-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, interpret it as −0x8000.
512-bit SVE
Take the minimum across corresponding active signed 16-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, interpret it as −0x8000.
Larger sizes
1024-bit SVE
Take the minimum across corresponding active signed 16-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, interpret it as −0x8000.
2048-bit SVE
Take the minimum across corresponding active signed 16-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, interpret it as −0x8000.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.