SVE Instruction List by Dougall Johnson
# SMINQV: Signed minimum reduction of quadword vector segments

SMINQV Vd.8H, Pg, Zn.H (SVE2.1 (SME2.1

## 128-bit SVE

Take the minimum across corresponding active signed 16-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, interpret it as 0x7FFF.

## 256-bit SVE

Take the minimum across corresponding active signed 16-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, interpret it as 0x7FFF.

## 512-bit SVE

Take the minimum across corresponding active signed 16-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, interpret it as 0x7FFF.

## Larger sizes

## 1024-bit SVE

Take the minimum across corresponding active signed 16-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, interpret it as 0x7FFF.

## 2048-bit SVE

Take the minimum across corresponding active signed 16-bit integer elements from each 128-bit segment of (1), storing the result in (3). For any element where the corresponding predicate bit in (2) is 0, interpret it as 0x7FFF.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.