SVE Instruction List by Dougall Johnson
SPLICE: Splice two vectors under predicate control
SPLICE Zd.H, Pv, { Zn1.H, Zn2.H } (SVE2 (SME
svbfloat16_t svsplice[_bf16](svbool_t pg, svbfloat16_t op1, svbfloat16_t op2)
svfloat16_t svsplice[_f16](svbool_t pg, svfloat16_t op1, svfloat16_t op2)
svint16_t svsplice[_s16](svbool_t pg, svint16_t op1, svint16_t op2)
svuint16_t svsplice[_u16](svbool_t pg, svuint16_t op1, svuint16_t op2)
128-bit SVE
Take the contiguous 16-bit lanes from (2), between the first and last corresponding set predicate bits in (1) (inclusive), and move them to the low lanes of (4). Any remaining high lanes in (4) are filled with the low elements from (3).
256-bit SVE
Take the contiguous 16-bit lanes from (2), between the first and last corresponding set predicate bits in (1) (inclusive), and move them to the low lanes of (4). Any remaining high lanes in (4) are filled with the low elements from (3).
512-bit SVE
Take the contiguous 16-bit lanes from (2), between the first and last corresponding set predicate bits in (1) (inclusive), and move them to the low lanes of (4). Any remaining high lanes in (4) are filled with the low elements from (3).
Larger sizes
1024-bit SVE
Take the contiguous 16-bit lanes from (2), between the first and last corresponding set predicate bits in (1) (inclusive), and move them to the low lanes of (4). Any remaining high lanes in (4) are filled with the low elements from (3).
2048-bit SVE
Take the contiguous 16-bit lanes from (2), between the first and last corresponding set predicate bits in (1) (inclusive), and move them to the low lanes of (4). Any remaining high lanes in (4) are filled with the low elements from (3).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.