SVE Instruction List by Dougall Johnson
SPLICE: Splice two vectors under predicate control
SPLICE Zd.D, Pv, { Zn1.D, Zn2.D } (SVE2 (SME
svfloat64_t svsplice[_f64](svbool_t pg, svfloat64_t op1, svfloat64_t op2)
svint64_t svsplice[_s64](svbool_t pg, svint64_t op1, svint64_t op2)
svuint64_t svsplice[_u64](svbool_t pg, svuint64_t op1, svuint64_t op2)
128-bit SVE
Take the contiguous 64-bit lanes from (2), between the first and last corresponding set predicate bits in (1) (inclusive), and move them to the low lanes of (4). Any remaining high lanes in (4) are filled with the low elements from (3).
256-bit SVE
Take the contiguous 64-bit lanes from (2), between the first and last corresponding set predicate bits in (1) (inclusive), and move them to the low lanes of (4). Any remaining high lanes in (4) are filled with the low elements from (3).
512-bit SVE
Take the contiguous 64-bit lanes from (2), between the first and last corresponding set predicate bits in (1) (inclusive), and move them to the low lanes of (4). Any remaining high lanes in (4) are filled with the low elements from (3).
Larger sizes
1024-bit SVE
Take the contiguous 64-bit lanes from (2), between the first and last corresponding set predicate bits in (1) (inclusive), and move them to the low lanes of (4). Any remaining high lanes in (4) are filled with the low elements from (3).
2048-bit SVE
Take the contiguous 64-bit lanes from (2), between the first and last corresponding set predicate bits in (1) (inclusive), and move them to the low lanes of (4). Any remaining high lanes in (4) are filled with the low elements from (3).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.