SVE Instruction List by Dougall Johnson
SQADD (vectors, predicated): Signed saturating addition (predicated)
SQADD Zdn.H, Pg/M, Zdn.H, Zm.H (SVE2 (SME
svint16_t svqadd[_s16]_m(svbool_t pg, svint16_t op1, svint16_t op2)
128-bit SVE
For each 16-bit integer set (3) to (1) + (2), with signed saturation to 0x7FFF or −0x8000 on overflow.
256-bit SVE
For each 16-bit integer set (3) to (1) + (2), with signed saturation to 0x7FFF or −0x8000 on overflow.
512-bit SVE
For each 16-bit integer set (3) to (1) + (2), with signed saturation to 0x7FFF or −0x8000 on overflow.
Larger sizes
1024-bit SVE
For each 16-bit integer set (3) to (1) + (2), with signed saturation to 0x7FFF or −0x8000 on overflow.
2048-bit SVE
For each 16-bit integer set (3) to (1) + (2), with signed saturation to 0x7FFF or −0x8000 on overflow.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.