See "SQRDMLAH (vectors)" in the exploration tools

SQRDMLAH (vectors): Signed saturating rounding doubling multiply-add high to accumulator (unpredicated)

SQRDMLAH Zda.D, Zn.D, Zm.D (SVE2 (SME

svint64_t svqrdmlah[_s64](svint64_t op1, svint64_t op2, svint64_t op3)

128-bit SVE

For each signed 64-bit integer set (4) to ( ( (1) << 63 ) + (2) * (3) + 0x4000000000000000 ) >> 63, with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000.

256-bit SVE

For each signed 64-bit integer set (4) to ( ( (1) << 63 ) + (2) * (3) + 0x4000000000000000 ) >> 63, with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000.

512-bit SVE

For each signed 64-bit integer set (4) to ( ( (1) << 63 ) + (2) * (3) + 0x4000000000000000 ) >> 63, with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000.

Larger sizes

1024-bit SVE

For each signed 64-bit integer set (4) to ( ( (1) << 63 ) + (2) * (3) + 0x4000000000000000 ) >> 63, with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000.

2048-bit SVE

For each signed 64-bit integer set (4) to ( ( (1) << 63 ) + (2) * (3) + 0x4000000000000000 ) >> 63, with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.