SVE Instruction List by Dougall Johnson
# SQRSHLR: Signed saturating rounding shift left reversed vectors (predicated)

SQRSHLR Zdn.D, Pg/M, Zdn.D, Zm.D (SVE2 (SME

## 128-bit SVE

Shift each signed 64-bit integer from (2) by the corresponding signed 64-bit integer from (1), rounding if shifting right, with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000 on overflow, setting (3) to the result. If (2) ≥ 0, the result is (2) << (1), otherwise it is ( (2) + ( 1 << ( −(1) − 1 ) ) ) >> −(1).

## 256-bit SVE

Shift each signed 64-bit integer from (2) by the corresponding signed 64-bit integer from (1), rounding if shifting right, with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000 on overflow, setting (3) to the result. If (2) ≥ 0, the result is (2) << (1), otherwise it is ( (2) + ( 1 << ( −(1) − 1 ) ) ) >> −(1).

## 512-bit SVE

Shift each signed 64-bit integer from (2) by the corresponding signed 64-bit integer from (1), rounding if shifting right, with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000 on overflow, setting (3) to the result. If (2) ≥ 0, the result is (2) << (1), otherwise it is ( (2) + ( 1 << ( −(1) − 1 ) ) ) >> −(1).

## Larger sizes

## 1024-bit SVE

Shift each signed 64-bit integer from (2) by the corresponding signed 64-bit integer from (1), rounding if shifting right, with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000 on overflow, setting (3) to the result. If (2) ≥ 0, the result is (2) << (1), otherwise it is ( (2) + ( 1 << ( −(1) − 1 ) ) ) >> −(1).

## 2048-bit SVE

Shift each signed 64-bit integer from (2) by the corresponding signed 64-bit integer from (1), rounding if shifting right, with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000 on overflow, setting (3) to the result. If (2) ≥ 0, the result is (2) << (1), otherwise it is ( (2) + ( 1 << ( −(1) − 1 ) ) ) >> −(1).

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.