SVE Instruction List by Dougall Johnson
See "SQRSHRUN" in the exploration tools

SQRSHRUN: Signed saturating rounding shift right unsigned narrow by immediate and interleave

SQRSHRUN Zd.H, { Zn1.S, Zn2.S }, #const (SVE2.1 (SME2

128-bit SVE

For each signed 32-bit integer element e from (1) and (2) compute ( e + ( 1 << ( const − 1 ) ) >> const, truncating to 16-bit with unsigned saturation to 0 (if e is negative) or 0xFFFF. Set the even 16-bit elements of (3) to the results from (1), and the odd 16-bit elements of (3) to the results from (2). The shift amount is limited to 1 ≤ const ≤ 16.

256-bit SVE

For each signed 32-bit integer element e from (1) and (2) compute ( e + ( 1 << ( const − 1 ) ) >> const, truncating to 16-bit with unsigned saturation to 0 (if e is negative) or 0xFFFF. Set the even 16-bit elements of (3) to the results from (1), and the odd 16-bit elements of (3) to the results from (2). The shift amount is limited to 1 ≤ const ≤ 16.

512-bit SVE

For each signed 32-bit integer element e from (1) and (2) compute ( e + ( 1 << ( const − 1 ) ) >> const, truncating to 16-bit with unsigned saturation to 0 (if e is negative) or 0xFFFF. Set the even 16-bit elements of (3) to the results from (1), and the odd 16-bit elements of (3) to the results from (2). The shift amount is limited to 1 ≤ const ≤ 16.

Larger sizes

1024-bit SVE

For each signed 32-bit integer element e from (1) and (2) compute ( e + ( 1 << ( const − 1 ) ) >> const, truncating to 16-bit with unsigned saturation to 0 (if e is negative) or 0xFFFF. Set the even 16-bit elements of (3) to the results from (1), and the odd 16-bit elements of (3) to the results from (2). The shift amount is limited to 1 ≤ const ≤ 16.

2048-bit SVE

For each signed 32-bit integer element e from (1) and (2) compute ( e + ( 1 << ( const − 1 ) ) >> const, truncating to 16-bit with unsigned saturation to 0 (if e is negative) or 0xFFFF. Set the even 16-bit elements of (3) to the results from (1), and the odd 16-bit elements of (3) to the results from (2). The shift amount is limited to 1 ≤ const ≤ 16.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.