SVE Instruction List by Dougall Johnson
SQRSHRUNT: Signed saturating rounding shift right unsigned narrow by immediate (top)
SQRSHRUNT Zd.B, Zn.H, #const (SVE2 (SME
svuint8_t svqrshrunt[_n_s16](svuint8_t even, svint16_t op1, uint64_t imm2)
128-bit SVE
For each signed 16-bit integer set the odd 8-bit elements of (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const, with unsigned saturation to 0 (if (1) is negative) or 0xFF, preserving even elements. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 8.
256-bit SVE
For each signed 16-bit integer set the odd 8-bit elements of (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const, with unsigned saturation to 0 (if (1) is negative) or 0xFF, preserving even elements. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 8.
512-bit SVE
For each signed 16-bit integer set the odd 8-bit elements of (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const, with unsigned saturation to 0 (if (1) is negative) or 0xFF, preserving even elements. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 8.
Larger sizes
1024-bit SVE
For each signed 16-bit integer set the odd 8-bit elements of (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const, with unsigned saturation to 0 (if (1) is negative) or 0xFF, preserving even elements. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 8.
2048-bit SVE
For each signed 16-bit integer set the odd 8-bit elements of (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const, with unsigned saturation to 0 (if (1) is negative) or 0xFF, preserving even elements. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 8.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.