SVE Instruction List by Dougall Johnson
# SQSHL (vectors): Signed saturating shift left by vector (predicated)

SQSHL Zdn.D, Pg/M, Zdn.D, Zm.D (SVE2 (SME

svint64_t svqshl[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2)

## 128-bit SVE

Shift each signed 64-bit integer from (1) by the corresponding signed 64-bit integer from (2), with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000 on overflow, setting (3) to the result. If (1) ≥ 0, this shifts left by (2), otherwise it shifts right by −(2).

## 256-bit SVE

Shift each signed 64-bit integer from (1) by the corresponding signed 64-bit integer from (2), with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000 on overflow, setting (3) to the result. If (1) ≥ 0, this shifts left by (2), otherwise it shifts right by −(2).

## 512-bit SVE

Shift each signed 64-bit integer from (1) by the corresponding signed 64-bit integer from (2), with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000 on overflow, setting (3) to the result. If (1) ≥ 0, this shifts left by (2), otherwise it shifts right by −(2).

## Larger sizes

## 1024-bit SVE

Shift each signed 64-bit integer from (1) by the corresponding signed 64-bit integer from (2), with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000 on overflow, setting (3) to the result. If (1) ≥ 0, this shifts left by (2), otherwise it shifts right by −(2).

## 2048-bit SVE

Shift each signed 64-bit integer from (1) by the corresponding signed 64-bit integer from (2), with signed saturation to 0x7FFFFFFFFFFFFFFF or −0x8000000000000000 on overflow, setting (3) to the result. If (1) ≥ 0, this shifts left by (2), otherwise it shifts right by −(2).

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.