SVE Instruction List by Dougall Johnson
See "SRHADD" in the exploration tools

SRHADD: Signed rounding halving addition

SRHADD Zdn.D, Pg/M, Zdn.D, Zm.D (SVE2 (SME
svint64_t svrhadd[_s64]_m(svbool_t pg, svint64_t op1, svint64_t op2)

128-bit SVE

For each signed 64-bit integer set (3) to ( (1) + (2) + 1 ) >> 1.

256-bit SVE

For each signed 64-bit integer set (3) to ( (1) + (2) + 1 ) >> 1.

512-bit SVE

For each signed 64-bit integer set (3) to ( (1) + (2) + 1 ) >> 1.
Larger sizes

1024-bit SVE

For each signed 64-bit integer set (3) to ( (1) + (2) + 1 ) >> 1.

2048-bit SVE

For each signed 64-bit integer set (3) to ( (1) + (2) + 1 ) >> 1.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.