SVE Instruction List by Dougall Johnson
# SRSHLR: Signed rounding shift left reversed vectors (predicated)

SRSHLR Zdn.S, Pg/M, Zdn.S, Zm.S (SVE2 (SME

## 128-bit SVE

Shift each signed 32-bit integer from (2) by the corresponding signed 32-bit integer from (1), rounding if shifting right, setting (3) to the result. If (2) ≥ 0, the result is (2) << (1), otherwise it is ( (2) + ( 1 << ( −(1) − 1 ) ) ) >> −(1).

## 256-bit SVE

Shift each signed 32-bit integer from (2) by the corresponding signed 32-bit integer from (1), rounding if shifting right, setting (3) to the result. If (2) ≥ 0, the result is (2) << (1), otherwise it is ( (2) + ( 1 << ( −(1) − 1 ) ) ) >> −(1).

## 512-bit SVE

Shift each signed 32-bit integer from (2) by the corresponding signed 32-bit integer from (1), rounding if shifting right, setting (3) to the result. If (2) ≥ 0, the result is (2) << (1), otherwise it is ( (2) + ( 1 << ( −(1) − 1 ) ) ) >> −(1).

## Larger sizes

## 1024-bit SVE

Shift each signed 32-bit integer from (2) by the corresponding signed 32-bit integer from (1), rounding if shifting right, setting (3) to the result. If (2) ≥ 0, the result is (2) << (1), otherwise it is ( (2) + ( 1 << ( −(1) − 1 ) ) ) >> −(1).

## 2048-bit SVE

Shift each signed 32-bit integer from (2) by the corresponding signed 32-bit integer from (1), rounding if shifting right, setting (3) to the result. If (2) ≥ 0, the result is (2) << (1), otherwise it is ( (2) + ( 1 << ( −(1) − 1 ) ) ) >> −(1).

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.