SVE Instruction List by Dougall Johnson
SRSRA: Signed rounding shift right and accumulate (immediate)
SRSRA Zda.D, Zn.D, #const (SVE2 (SME
svint64_t svrsra[_n_s64](svint64_t op1, svint64_t op2, uint64_t imm3)
128-bit SVE
For each 64-bit signed integer set (3) to (1) + ( (2) + ( 1 << ( const − 1 ) ) >> const. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 64.
256-bit SVE
For each 64-bit signed integer set (3) to (1) + ( (2) + ( 1 << ( const − 1 ) ) >> const. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 64.
512-bit SVE
For each 64-bit signed integer set (3) to (1) + ( (2) + ( 1 << ( const − 1 ) ) >> const. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 64.
Larger sizes
1024-bit SVE
For each 64-bit signed integer set (3) to (1) + ( (2) + ( 1 << ( const − 1 ) ) >> const. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 64.
2048-bit SVE
For each 64-bit signed integer set (3) to (1) + ( (2) + ( 1 << ( const − 1 ) ) >> const. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 64.
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.