SVE Instruction List by Dougall Johnson
ST1D (scalar plus immediate, consecutive registers): Contiguous store of doublewords from multiple consecutive vectors (immediate index)
ST1D { Zt1.D, Zt2.D, Zt3.D, Zt4.D }, PNg, [Xn{, #imm, MUL VL}] (SVE2.1 (SME2+S
128-bit SVE
Store 64-bit values from the four consecutive registers (2), (3), (4), and (5) to the memory operand (6). After decoding the predicate (1) from its predicate-as-counter representation to a quadruple-length predicate, if the predicate bit corresponding to an element is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged. The first register number (2) must be divisible by four.
256-bit SVE
Store 64-bit values from the four consecutive registers (2), (3), (4), and (5) to the memory operand (6). After decoding the predicate (1) from its predicate-as-counter representation to a quadruple-length predicate, if the predicate bit corresponding to an element is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged. The first register number (2) must be divisible by four.
512-bit SVE
Store 64-bit values from the four consecutive registers (2), (3), (4), and (5) to the memory operand (6). After decoding the predicate (1) from its predicate-as-counter representation to a quadruple-length predicate, if the predicate bit corresponding to an element is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged. The first register number (2) must be divisible by four.
Larger sizes
1024-bit SVE
Store 64-bit values from the four consecutive registers (2), (3), (4), and (5) to the memory operand (6). After decoding the predicate (1) from its predicate-as-counter representation to a quadruple-length predicate, if the predicate bit corresponding to an element is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged. The first register number (2) must be divisible by four.
2048-bit SVE
Store 64-bit values from the four consecutive registers (2), (3), (4), and (5) to the memory operand (6). After decoding the predicate (1) from its predicate-as-counter representation to a quadruple-length predicate, if the predicate bit corresponding to an element is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged. The first register number (2) must be divisible by four.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.