SVE Instruction List by Dougall Johnson
ST1D (scalar plus scalar, single register): Contiguous store doublewords from vector (scalar index)
ST1D { Zt.Q }, Pg, [Xn, Xm, LSL #3] (SVE2.1+NS
128-bit SVE
Truncate each active 128-bit element of (1) to a 64-bit value, and store them to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
256-bit SVE
Truncate each active 128-bit element of (1) to a 64-bit value, and store them to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
512-bit SVE
Truncate each active 128-bit element of (1) to a 64-bit value, and store them to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
Larger sizes
1024-bit SVE
Truncate each active 128-bit element of (1) to a 64-bit value, and store them to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
2048-bit SVE
Truncate each active 128-bit element of (1) to a 64-bit value, and store them to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.