SVE Instruction List by Dougall Johnson
ST1H (scalar plus scalar, consecutive registers): Contiguous store of halfwords from multiple consecutive vectors (scalar index)
ST1H { Zt1.H, Zt2.H }, PNg, [Xn, Xm, LSL #1] (SVE2.1 (SME2+S
128-bit SVE
Store 16-bit values from the two consecutive registers (2) and (3) to the memory operand (4). After decoding the predicate (1) from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged. The first register number (2) must be divisible by two.
256-bit SVE
Store 16-bit values from the two consecutive registers (2) and (3) to the memory operand (4). After decoding the predicate (1) from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged. The first register number (2) must be divisible by two.
512-bit SVE
Store 16-bit values from the two consecutive registers (2) and (3) to the memory operand (4). After decoding the predicate (1) from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged. The first register number (2) must be divisible by two.
Larger sizes
1024-bit SVE
Store 16-bit values from the two consecutive registers (2) and (3) to the memory operand (4). After decoding the predicate (1) from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged. The first register number (2) must be divisible by two.
2048-bit SVE
Store 16-bit values from the two consecutive registers (2) and (3) to the memory operand (4). After decoding the predicate (1) from its predicate-as-counter representation to a double-length predicate, if the predicate bit corresponding to an element is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged. The first register number (2) must be divisible by two.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.