SVE Instruction List by Dougall Johnson
ST1H (scalar plus immediate, single register): Contiguous store halfwords from vector (immediate index)
ST1H { Zt.H }, Pg, [Xn{, #imm, MUL VL}] (SVE (SME
void svst1_vnum[_bf16](svbool_t pg, bfloat16_t *base, int64_t vnum, svbfloat16_t data)
void svst1_vnum[_f16](svbool_t pg, float16_t *base, int64_t vnum, svfloat16_t data)
void svst1_vnum[_s16](svbool_t pg, int16_t *base, int64_t vnum, svint16_t data)
void svst1_vnum[_u16](svbool_t pg, uint16_t *base, int64_t vnum, svuint16_t data)
128-bit SVE
Store each active 16-bit element of (1) to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
256-bit SVE
Store each active 16-bit element of (1) to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
512-bit SVE
Store each active 16-bit element of (1) to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
Larger sizes
1024-bit SVE
Store each active 16-bit element of (1) to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
2048-bit SVE
Store each active 16-bit element of (1) to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.