SVE Instruction List by Dougall Johnson
ST1H (scalar plus immediate, single register): Contiguous store halfwords from vector (immediate index)
ST1H { Zt.D }, Pg, [Xn{, #imm, MUL VL}] (SVE (SME
void svst1h_vnum[_s64](svbool_t pg, int16_t *base, int64_t vnum, svint64_t data)
void svst1h_vnum[_u64](svbool_t pg, uint16_t *base, int64_t vnum, svuint64_t data)
128-bit SVE
Truncate each active 64-bit element of (1) to a 16-bit value, and store them to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
256-bit SVE
Truncate each active 64-bit element of (1) to a 16-bit value, and store them to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
512-bit SVE
Truncate each active 64-bit element of (1) to a 16-bit value, and store them to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
Larger sizes
1024-bit SVE
Truncate each active 64-bit element of (1) to a 16-bit value, and store them to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
2048-bit SVE
Truncate each active 64-bit element of (1) to a 16-bit value, and store them to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.