SVE Instruction List by Dougall Johnson
ST1H (scalar plus scalar, single register): Contiguous store halfwords from vector (scalar index)
ST1H { Zt.H }, Pg, [Xn, Xm, LSL #1] (SVE (SME
void svst1[_bf16](svbool_t pg, bfloat16_t *base, svbfloat16_t data)
void svst1[_f16](svbool_t pg, float16_t *base, svfloat16_t data)
void svst1[_s16](svbool_t pg, int16_t *base, svint16_t data)
void svst1[_u16](svbool_t pg, uint16_t *base, svuint16_t data)
128-bit SVE
Store each active 16-bit element of (1) to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
256-bit SVE
Store each active 16-bit element of (1) to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
512-bit SVE
Store each active 16-bit element of (1) to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
Larger sizes
1024-bit SVE
Store each active 16-bit element of (1) to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
2048-bit SVE
Store each active 16-bit element of (1) to the memory operand (3). If the corresponding predicate bit from (2) is zero, that store is skipped, and cannot cause a fault, and the corresponding value in memory is unchanged.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.