SVE Instruction List by Dougall Johnson
ST3H (scalar plus immediate): Contiguous store three-halfword structures from three vectors (immediate index)
ST3H { Zt1.H, Zt2.H, Zt3.H }, Pg, [Xn{, #imm, MUL VL}] (SVE (SME
128-bit SVE
Interleave 16-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.
256-bit SVE
Interleave 16-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.
512-bit SVE
Interleave 16-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.
Larger sizes
1024-bit SVE
Interleave 16-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.
2048-bit SVE
Interleave 16-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.