SVE Instruction List by Dougall Johnson
ST3Q (scalar plus scalar): Contiguous store three-quadword structures from three vectors (scalar index)
ST3Q { Zt1.Q, Zt2.Q, Zt3.Q }, Pg, [Xn, Xm, LSL #4] (SVE2.1 (SME2.1
128-bit SVE
Interleave 128-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.
256-bit SVE
Interleave 128-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.
512-bit SVE
Interleave 128-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.
Larger sizes
1024-bit SVE
Interleave 128-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.
2048-bit SVE
Interleave 128-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.