SVE Instruction List by Dougall Johnson
See "ST3W (scalar plus immediate)" in the exploration tools

ST3W (scalar plus immediate): Contiguous store three-word structures from three vectors (immediate index)

ST3W { Zt1.S, Zt2.S, Zt3.S }, Pg, [Xn{, #imm, MUL VL}] (SVE (SME
void svst3_vnum[_f32](svbool_t pg, float32_t *base, int64_t vnum, svfloat32x3_t data)
void svst3_vnum[_s32](svbool_t pg, int32_t *base, int64_t vnum, svint32x3_t data)
void svst3_vnum[_u32](svbool_t pg, uint32_t *base, int64_t vnum, svuint32x3_t data)

128-bit SVE

Interleave 32-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.

256-bit SVE

Interleave 32-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.

512-bit SVE

Interleave 32-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.

Larger sizes

1024-bit SVE

Interleave 32-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.

2048-bit SVE

Interleave 32-bit elements from three consecutive registers (2), (3), and (4), and store them to the memory operand (5). If the predicate bit from (1) corresponding to an element in (2), (3), and (4) is zero, those three contiguous stores are skipped, and cannot cause a fault, and the corresponding values in memory are unchanged.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.