TBL: Programmable table lookup in one or two vector table (zeroing)

TBL Zd.H, { Zn1.H, Zn2.H }, Zm.H (SVE2 (SME

svbfloat16_t svtbl2[_bf16](svbfloat16x2_t data, svuint16_t indices)

svfloat16_t svtbl2[_f16](svfloat16x2_t data, svuint16_t indices)

svint16_t svtbl2[_s16](svint16x2_t data, svuint16_t indices)

svuint16_t svtbl2[_u16](svuint16x2_t data, svuint16_t indices)

128-bit SVE

For each 16-bit index from (2), if 0 ≤ index < 16, set (3) to the 16-bit element at that index in the two-register table (1), otherwise set (3) to zero.

256-bit SVE

For each 16-bit index from (2), if 0 ≤ index < 32, set (3) to the 16-bit element at that index in the two-register table (1), otherwise set (3) to zero.

512-bit SVE

For each 16-bit index from (2), if 0 ≤ index < 64, set (3) to the 16-bit element at that index in the two-register table (1), otherwise set (3) to zero.

Larger sizes

1024-bit SVE

For each 16-bit index from (2), if 0 ≤ index < 128, set (3) to the 16-bit element at that index in the two-register table (1), otherwise set (3) to zero.

2048-bit SVE

For each 16-bit index from (2), set (3) to the 16-bit element at that index in the two-register table (1). Optional zeroing is not possible on 2048-bit SVE.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.