TBL: Programmable table lookup in one or two vector table (zeroing)

TBL Zd.D, { Zn1.D, Zn2.D }, Zm.D (SVE2 (SME

svfloat64_t svtbl2[_f64](svfloat64x2_t data, svuint64_t indices)

svint64_t svtbl2[_s64](svint64x2_t data, svuint64_t indices)

svuint64_t svtbl2[_u64](svuint64x2_t data, svuint64_t indices)

128-bit SVE

For each 64-bit index from (2), if 0 ≤ index < 4, set (3) to the 64-bit element at that index in the two-register table (1), otherwise set (3) to zero.

256-bit SVE

For each 64-bit index from (2), if 0 ≤ index < 8, set (3) to the 64-bit element at that index in the two-register table (1), otherwise set (3) to zero.

512-bit SVE

For each 64-bit index from (2), if 0 ≤ index < 16, set (3) to the 64-bit element at that index in the two-register table (1), otherwise set (3) to zero.

Larger sizes

1024-bit SVE

For each 64-bit index from (2), if 0 ≤ index < 32, set (3) to the 64-bit element at that index in the two-register table (1), otherwise set (3) to zero.

2048-bit SVE

For each 64-bit index from (2), if 0 ≤ index < 64, set (3) to the 64-bit element at that index in the two-register table (1), otherwise set (3) to zero.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.