TBLQ: Programmable table lookup within each quadword vector segment (zeroing)

TBLQ Zd.D, { Zn.D }, Zm.D (SVE2.1 (SME2.1

128-bit SVE

Within each 128-bit segment, for each 64-bit index from (2), if 0 ≤ index < 2, set (3) to the 64-bit element at that index in the segment from (1), otherwise set (3) to zero.

256-bit SVE

Within each 128-bit segment, for each 64-bit index from (2), if 0 ≤ index < 2, set (3) to the 64-bit element at that index in the segment from (1), otherwise set (3) to zero.

512-bit SVE

Within each 128-bit segment, for each 64-bit index from (2), if 0 ≤ index < 2, set (3) to the 64-bit element at that index in the segment from (1), otherwise set (3) to zero.

Larger sizes

1024-bit SVE

Within each 128-bit segment, for each 64-bit index from (2), if 0 ≤ index < 2, set (3) to the 64-bit element at that index in the segment from (1), otherwise set (3) to zero.

2048-bit SVE

Within each 128-bit segment, for each 64-bit index from (2), if 0 ≤ index < 2, set (3) to the 64-bit element at that index in the segment from (1), otherwise set (3) to zero.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.