SVE Instruction List by Dougall Johnson
See "TRN1, TRN2 (vectors)" in the exploration tools

TRN1 (vectors): Interleave even elements from two vectors

TRN1 Zd.H, Zn.H, Zm.H (SVE (SME
svbfloat16_t svtrn1[_bf16](svbfloat16_t op1, svbfloat16_t op2)
svfloat16_t svtrn1[_f16](svfloat16_t op1, svfloat16_t op2)
svint16_t svtrn1[_s16](svint16_t op1, svint16_t op2)
svuint16_t svtrn1[_u16](svuint16_t op1, svuint16_t op2)

128-bit SVE

Set (3) to the interleaved even 16-bit elements from (1) and (2).

256-bit SVE

Set (3) to the interleaved even 16-bit elements from (1) and (2).

512-bit SVE

Set (3) to the interleaved even 16-bit elements from (1) and (2).
Larger sizes

1024-bit SVE

Set (3) to the interleaved even 16-bit elements from (1) and (2).

2048-bit SVE

Set (3) to the interleaved even 16-bit elements from (1) and (2).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.