SVE Instruction List by Dougall Johnson
TRN1 (vectors): Interleave even elements from two vectors
TRN1 Zd.S, Zn.S, Zm.S (SVE (SME
svfloat32_t svtrn1[_f32](svfloat32_t op1, svfloat32_t op2)
svint32_t svtrn1[_s32](svint32_t op1, svint32_t op2)
svuint32_t svtrn1[_u32](svuint32_t op1, svuint32_t op2)
128-bit SVE
Set (3) to the interleaved even 32-bit elements from (1) and (2).
256-bit SVE
Set (3) to the interleaved even 32-bit elements from (1) and (2).
512-bit SVE
Set (3) to the interleaved even 32-bit elements from (1) and (2).
Larger sizes
1024-bit SVE
Set (3) to the interleaved even 32-bit elements from (1) and (2).
2048-bit SVE
Set (3) to the interleaved even 32-bit elements from (1) and (2).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.