SVE Instruction List by Dougall Johnson
TRN1 (vectors): Interleave even elements from two vectors
TRN1 Zd.D, Zn.D, Zm.D (SVE (SME
svfloat64_t svtrn1[_f64](svfloat64_t op1, svfloat64_t op2)
svint64_t svtrn1[_s64](svint64_t op1, svint64_t op2)
svuint64_t svtrn1[_u64](svuint64_t op1, svuint64_t op2)
128-bit SVE
Set (3) to the interleaved even 64-bit elements from (1) and (2).
256-bit SVE
Set (3) to the interleaved even 64-bit elements from (1) and (2).
512-bit SVE
Set (3) to the interleaved even 64-bit elements from (1) and (2).
Larger sizes
1024-bit SVE
Set (3) to the interleaved even 64-bit elements from (1) and (2).
2048-bit SVE
Set (3) to the interleaved even 64-bit elements from (1) and (2).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.