SVE Instruction List by Dougall Johnson
See "TRN1, TRN2 (vectors)" in the exploration tools

TRN2 (vectors): Interleave odd elements from two vectors

TRN2 Zd.Q, Zn.Q, Zm.Q (SVE+F64MM+NS
svbfloat16_t svtrn2q[_bf16](svbfloat16_t op1, svbfloat16_t op2)
svfloat16_t svtrn2q[_f16](svfloat16_t op1, svfloat16_t op2)
svfloat32_t svtrn2q[_f32](svfloat32_t op1, svfloat32_t op2)
svfloat64_t svtrn2q[_f64](svfloat64_t op1, svfloat64_t op2)
svint8_t svtrn2q[_s8](svint8_t op1, svint8_t op2)
svint16_t svtrn2q[_s16](svint16_t op1, svint16_t op2)
svint32_t svtrn2q[_s32](svint32_t op1, svint32_t op2)
svint64_t svtrn2q[_s64](svint64_t op1, svint64_t op2)
svuint8_t svtrn2q[_u8](svuint8_t op1, svuint8_t op2)
svuint16_t svtrn2q[_u16](svuint16_t op1, svuint16_t op2)
svuint32_t svtrn2q[_u32](svuint32_t op1, svuint32_t op2)
svuint64_t svtrn2q[_u64](svuint64_t op1, svuint64_t op2)

128-bit SVE

This operation is undefined for 128-bit SVE.

256-bit SVE

Set (3) to the interleaved odd 128-bit elements from (1) and (2).

512-bit SVE

Set (3) to the interleaved odd 128-bit elements from (1) and (2).

Larger sizes

1024-bit SVE

Set (3) to the interleaved odd 128-bit elements from (1) and (2).

2048-bit SVE

Set (3) to the interleaved odd 128-bit elements from (1) and (2).

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.