SVE Instruction List by Dougall Johnson
UQRSHL: Unsigned saturating rounding shift left by vector (predicated)
UQRSHL Zdn.H, Pg/M, Zdn.H, Zm.H (SVE2 (SME
svuint16_t svqrshl[_u16]_m(svbool_t pg, svuint16_t op1, svint16_t op2)
128-bit SVE
Shift each unsigned 16-bit integer from (1) by the corresponding signed 16-bit integer from (2), rounding if shifting right, with unsigned saturation to 0xFFFF on overflow, setting (3) to the result. If (2) ≥ 0, the result is (1) << (2), otherwise it is ( (1) + ( 1 << ( −(2) − 1 ) ) ) >> −(2).
256-bit SVE
Shift each unsigned 16-bit integer from (1) by the corresponding signed 16-bit integer from (2), rounding if shifting right, with unsigned saturation to 0xFFFF on overflow, setting (3) to the result. If (2) ≥ 0, the result is (1) << (2), otherwise it is ( (1) + ( 1 << ( −(2) − 1 ) ) ) >> −(2).
512-bit SVE
Shift each unsigned 16-bit integer from (1) by the corresponding signed 16-bit integer from (2), rounding if shifting right, with unsigned saturation to 0xFFFF on overflow, setting (3) to the result. If (2) ≥ 0, the result is (1) << (2), otherwise it is ( (1) + ( 1 << ( −(2) − 1 ) ) ) >> −(2).
Larger sizes
1024-bit SVE
Shift each unsigned 16-bit integer from (1) by the corresponding signed 16-bit integer from (2), rounding if shifting right, with unsigned saturation to 0xFFFF on overflow, setting (3) to the result. If (2) ≥ 0, the result is (1) << (2), otherwise it is ( (1) + ( 1 << ( −(2) − 1 ) ) ) >> −(2).
2048-bit SVE
Shift each unsigned 16-bit integer from (1) by the corresponding signed 16-bit integer from (2), rounding if shifting right, with unsigned saturation to 0xFFFF on overflow, setting (3) to the result. If (2) ≥ 0, the result is (1) << (2), otherwise it is ( (1) + ( 1 << ( −(2) − 1 ) ) ) >> −(2).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.