SVE Instruction List by Dougall Johnson
See "UQRSHRNT" in the exploration tools

UQRSHRNT: Unsigned saturating rounding shift right narrow by immediate (top)

UQRSHRNT Zd.H, Zn.S, #const (SVE2 (SME
svuint16_t svqrshrnt[_n_u32](svuint16_t even, svuint32_t op1, uint64_t imm2)

128-bit SVE

For each unsigned 32-bit integer set the odd 16-bit elements of (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const, truncating with unsigned saturation to 0xFFFF, preserving even elements. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 16.

256-bit SVE

For each unsigned 32-bit integer set the odd 16-bit elements of (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const, truncating with unsigned saturation to 0xFFFF, preserving even elements. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 16.

512-bit SVE

For each unsigned 32-bit integer set the odd 16-bit elements of (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const, truncating with unsigned saturation to 0xFFFF, preserving even elements. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 16.

Larger sizes

1024-bit SVE

For each unsigned 32-bit integer set the odd 16-bit elements of (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const, truncating with unsigned saturation to 0xFFFF, preserving even elements. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 16.

2048-bit SVE

For each unsigned 32-bit integer set the odd 16-bit elements of (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const, truncating with unsigned saturation to 0xFFFF, preserving even elements. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 16.

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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.