SVE Instruction List by Dougall Johnson
URSHR: Unsigned rounding shift right by immediate
URSHR Zdn.D, Pg/M, Zdn.D, #const (SVE2 (SME
svuint64_t svrshr[_n_u64]_m(svbool_t pg, svuint64_t op1, uint64_t imm2)
128-bit SVE
For each 64-bit unsigned integer set (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 64.
256-bit SVE
For each 64-bit unsigned integer set (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 64.
512-bit SVE
For each 64-bit unsigned integer set (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 64.
Larger sizes
1024-bit SVE
For each 64-bit unsigned integer set (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 64.
2048-bit SVE
For each 64-bit unsigned integer set (2) to ( (1) + ( 1 << ( const − 1 ) ) >> const. This is the same as a regular shift, but with result incremented if the most-significant bit that was shifted out was set. The shift amount is limited to 1 ≤ const ≤ 64.
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.