SVE Instruction List by Dougall Johnson
UZP1 (vectors): Concatenate even elements from two vectors
UZP1 Zd.D, Zn.D, Zm.D (SVE (SME
svfloat64_t svuzp1[_f64](svfloat64_t op1, svfloat64_t op2)
svint64_t svuzp1[_s64](svint64_t op1, svint64_t op2)
svuint64_t svuzp1[_u64](svuint64_t op1, svuint64_t op2)
128-bit SVE
Set the low half of (3) to the even 64-bit elements from (1), and the high half of (3) to the even 64-bit elements from (2).
256-bit SVE
Set the low half of (3) to the even 64-bit elements from (1), and the high half of (3) to the even 64-bit elements from (2).
512-bit SVE
Set the low half of (3) to the even 64-bit elements from (1), and the high half of (3) to the even 64-bit elements from (2).
Larger sizes
1024-bit SVE
Set the low half of (3) to the even 64-bit elements from (1), and the high half of (3) to the even 64-bit elements from (2).
2048-bit SVE
Set the low half of (3) to the even 64-bit elements from (1), and the high half of (3) to the even 64-bit elements from (2).
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Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.