SVE Instruction List by Dougall Johnson
ZIP1 (vectors): Interleave elements from low halves of two vectors
ZIP1 Zd.D, Zn.D, Zm.D (SVE (SME
svfloat64_t svzip1[_f64](svfloat64_t op1, svfloat64_t op2)
svint64_t svzip1[_s64](svint64_t op1, svint64_t op2)
svuint64_t svzip1[_u64](svuint64_t op1, svuint64_t op2)
128-bit SVE
Set (3) to the interleaved 64-bit elements from the low halves of (1) and (2).
256-bit SVE
Set (3) to the interleaved 64-bit elements from the low halves of (1) and (2).
512-bit SVE
Set (3) to the interleaved 64-bit elements from the low halves of (1) and (2).
Larger sizes
1024-bit SVE
Set (3) to the interleaved 64-bit elements from the low halves of (1) and (2).
2048-bit SVE
Set (3) to the interleaved 64-bit elements from the low halves of (1) and (2).
Report mistakes or give feedback
Inspired by and based on the x86/x64 SIMD Instruction List by Daytime.