Firestorm: ADCS (32-bit) measurements

Code:

  adcs w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	73	2	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	3	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	2	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	8	0	156	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036
1004	1035	7	0	61	917	25	1000	1000	1000	62250	1035	1035	805	3	882	1000	1000	3000	1035	40	1	1	1001	1000	0	0	0	73	1	27	1	1	993	1000	1000	1036	1036	1036	1036	1036

Test 2: Latency 1->2

Code:

  adcs w0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	84	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	78	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	3	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	1	3	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	78	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	6	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	9	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	3	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	0	0	710	1	27	1	1	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	96	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	678	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	12	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	595	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10085	40	1	1	10021	10	9	10	10010	10	0	0	0	0	657	2	27	3	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	1040	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	82	9918	48	10010	10010	10010	647246	1	49	6955	10035	10081	8678	3	8754	10093	10213	30020	10035	40	1	1	10021	10	9	10	10010	10	0	2	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	21	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	12	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	36	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 3: Latency 1->3

Code:

  adcs w0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	120	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	3	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	1	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	2	3	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	75	0	61	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036
10204	10035	76	0	251	9920	25	10100	10100	10100	647152	0	49	6955	10035	10035	8656	3	8732	10100	10200	30200	10035	40	1	1	10201	100	99	100	10100	100	0	0	710	2	27	2	2	9995	10000	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	2	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	3	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	3	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	1	3	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	3	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	38	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	24	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	9	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	3	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	61	9918	25	10010	10010	10010	647246	1	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	76	0	0	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	1	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036
10024	10035	75	0	1	0	61	9918	25	10010	10010	10010	647246	0	49	6955	10035	10035	8678	3	8754	10010	10020	30020	10035	40	1	1	10021	10	9	10	10010	10	0	0	640	2	27	2	2	9997	10000	10010	10036	10036	10036	10036	10036

Test 4: Latency 1->4

Chain cycles: 1

Code:

  adcs w0, w1, w2
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	0	0	0	0	0	48	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	9	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20067	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	30	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	0	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036
20204	20035	150	0	0	0	0	0	0	0	61	19926	25	20200	20200	20200	1297650	1	49	16955	20035	20035	17406	3	17481	20200	20200	40200	20035	64	1	1	20201	100	99	20100	0	0	0	0	0	0	0	0	1310	1	28	1	1	19992	20100	10100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	144	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	1270	5	27	1	2	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	2	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	1	324	88	165	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	1	0	3	1270	1	27	2	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20080	64	4	1	20021	10	9	20010	0	1	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	24	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	1	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	61	19918	109	20020	20064	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	1	0	6	1270	1	27	2	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	15	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036
20024	20035	150	0	12	0	61	19918	25	20020	20020	20020	1297297	49	16955	20035	20035	17428	3	17504	20020	20020	40020	20035	64	1	1	20021	10	9	20010	0	0	0	0	1270	1	27	1	1	19995	20010	10010	20036	20036	20036	20036	20036

Test 5: Latency 4->2

Chain cycles: 1

Code:

  adcs w0, w1, w2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	3	1	1	1	1319	1	16	1	1	20014	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1320	1	16	1	1	20014	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	1	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1320	1	16	1	1	20014	20000	20100	20036	20036	20036	20036	20036
20204	20067	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1320	1	16	1	1	20014	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	3	1	1	1	1320	1	16	1	1	20014	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1319	1	16	1	1	20014	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	3163	1	1	1	1320	1	16	1	1	20014	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1320	1	16	1	1	20014	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1320	1	16	1	1	20014	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	66	19930	25	20100	20100	20112	1297233	1	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	0	0	1	1	1	1320	1	16	1	1	20014	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	4	27	3	4	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	82	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	3	27	4	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	3	0	1270	4	27	4	4	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	3849	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	3	27	4	4	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	1	1270	4	27	4	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	4	27	4	4	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	3	27	4	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	2	2	0	0	1270	3	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20010	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1270	4	27	3	3	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	61	19918	25	20010	20032	20010	1297247	49	16955	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	99	0	1270	4	27	4	3	19995	20000	20010	20036	20036	20036	20036	20036

Test 6: Latency 4->3

Chain cycles: 1

Code:

  adcs w0, w1, w2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	117	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	102	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	149	1	1	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	8	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	87	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1319	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	536	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17485	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	6	1	1	1	1320	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036
20204	20035	150	1	1	0	0	61	19930	25	20100	20100	20112	1297233	49	16955	20035	20035	17425	7	17486	20112	20224	40248	20035	64	1	1	20201	100	99	100	20100	10100	0	0	0	1	1	1	1320	1	16	1	1	20015	20000	20100	20036	20036	20036	20036	20036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
20024	20035	150	0	0	0	0	0	0	0	0	0	189	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	42	0	3	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	44	0	63	0	1270	2	27	3	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	0	49	16955	0	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	1	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	41	0	180	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	35	0	111	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	150	0	0	0	0	0	0	0	0	0	61	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036
20024	20035	149	0	0	0	0	0	0	0	0	0	187	19918	25	20010	20010	20010	1297247	1	49	16955	0	20035	20035	17428	3	17504	20010	20020	40020	20035	64	1	1	20021	10	9	10	20010	10010	0	0	0	0	0	0	0	0	1270	2	27	2	2	19995	20000	20010	20036	20036	20036	20036	20036

Test 7: Latency 4->4

Code:

  adcs w0, w1, w2

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10067	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	16	0	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8736	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	16	0	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	9	0	1	1	1	719	16	0	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	16	0	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10085	75	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8736	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	16	0	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	16	0	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	3	0	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	16	0	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	77	0	0	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8736	10210	10320	30272	10035	40	1	1	10201	100	99	10100	0	0	0	18	0	1	1	1	720	16	0	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	1	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	0	0	1	1	1	720	16	0	0	10013	10100	10100	10036	10036	10036	10036	10036
10204	10035	75	0	0	0	61	9927	25	10200	10200	10210	647712	0	49	6955	10035	10035	8673	8	8735	10210	10224	30272	10035	40	1	1	10201	100	99	10100	0	0	0	21	0	1	1	1	720	16	0	0	10013	10100	10100	10036	10036	10036	10036	10036

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0035

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	1e	1f	3f	4d	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst int alu (97)	l1d tlb access (a0)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
10024	10035	75	0	0	0	171	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	0	49	6956	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	640	3	27	2	2	9997	10010	10010	10084	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	1	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	2	2	0	640	3	27	2	2	10031	10032	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	1	0	0	61	9918	25	10020	10020	10020	647296	1	49	7003	10082	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	3	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	12	0	61	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	640	3	27	3	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	15	176	61	9918	25	10020	10020	10020	647296	0	49	6956	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036
10024	10035	75	0	0	0	0	0	61	9918	25	10020	10020	10020	647296	0	49	6955	10035	10035	8678	3	8754	10020	10020	30020	10035	40	1	1	10021	10	9	10010	0	0	0	640	2	27	2	2	9997	10010	10010	10036	10036	10036	10036	10036

Test 8: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  adcs w0, w8, w9
  ands xzr, xzr, xzr
  adcs w1, w8, w9
  ands xzr, xzr, xzr
  adcs w2, w8, w9
  ands xzr, xzr, xzr
  adcs w3, w8, w9
  ands xzr, xzr, xzr
  adcs w4, w8, w9
  ands xzr, xzr, xzr
  adcs w5, w8, w9
  ands xzr, xzr, xzr
  adcs w6, w8, w9
  ands xzr, xzr, xzr
  adcs w7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
160204	53409	400	0	0	0	0	0	528	28	160120	160120	160128	1063738	49	50329	53409	53408	33347	7	33357	160128	160240	240260	53409	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	1	1	1	10120	1	16	0	0	53406	160020	80100	53457	53410	53410	53410	53409
160204	53409	399	0	0	0	0	0	181	28	160120	160120	160128	1063738	49	50328	53409	53409	33347	7	33357	160128	160240	240260	53409	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	1	1	1	10120	0	16	0	0	53406	160020	80100	53410	53409	53409	53410	53410
160204	53408	400	0	0	0	3	0	160	27	160120	160120	160128	1063738	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	190	25	160100	160100	160100	1063588	49	50324	53404	53404	33339	3	33359	160100	160200	240368	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	0	0	10110	1	19	1	1	53437	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	146	25	160100	160100	160100	1063588	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	3	3	0	0	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	1	0	0	0	0	37	25	160100	160100	160100	1063588	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	146	25	160100	160100	160100	1063588	49	50324	53404	53404	33339	8	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	2	0	0	0	0	0	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	400	0	0	0	0	0	169	25	160100	160100	160100	1063588	49	50324	53404	53404	33339	3	33390	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	2	0	0	0	0	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	399	0	0	0	0	0	295	25	160100	160100	160100	1063588	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405
160204	53404	399	0	0	0	0	0	146	25	160100	160100	160100	1063588	49	50324	53404	53404	33339	3	33359	160100	160200	240200	53404	52	1	1	160201	100	99	100	160100	100	0	0	0	0	0	0	0	0	0	0	10110	1	19	1	1	53401	160000	80100	53405	53405	53405	53405	53405

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6672

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	5f	60	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
160024	53390	400	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	6	1	2	12	19	6	2	1	5	3	53370	160000	40	18	80010	53375	53375	53375	53375	53375
160024	53374	399	0	0	49	25	160010	160010	160010	1029388	1	0	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10024	6	2	2	6	19	4	1	2	3	9	53370	160000	40	9	80010	53375	53375	53375	53375	53375
160024	53374	399	0	0	49	25	160010	160010	160010	1029388	0	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	3	2	2	9	19	4	1	1	3	5	53370	160000	20	9	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	3	1	1	3	19	4	1	1	3	9	53370	160000	20	9	80010	53375	53375	53375	53375	53375
160024	53374	399	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	3	1	1	3	19	4	1	2	5	3	53370	160000	20	9	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	3	1	1	3	19	2	1	1	4	11	53370	160000	20	9	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	3	1	1	8	19	4	1	1	3	5	53370	160000	20	9	80010	53375	53375	53375	53375	53375
160024	53374	400	0	0	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	3	1	1	3	19	2	1	1	5	10	53370	160000	20	9	80010	53375	53375	53375	53375	53375
160024	53374	400	0	9	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	3	1	1	5	19	2	1	1	5	11	53370	160000	20	9	80010	53375	53375	53375	53375	53375
160024	53374	400	0	18	43	25	160010	160010	160010	1029388	1	1	49	50294	53374	53374	33331	3	33351	160010	160020	240020	53374	52	1	1	160021	10	9	10	160010	10	0	0	0	0	10022	3	1	1	5	19	2	1	1	9	5	53370	160000	20	9	80010	53375	53375	53375	53375	53375

Test 9: throughput

Count: 4

Code:

  fcmp s0, s0
  adcs w0, w4, w5
  adcs w1, w4, w5
  adcs w2, w4, w5
  adcs w3, w4, w5

Initialization

  mov x4, 5
  mov x5, 6
  mov x6, 7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3353

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4d	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50204	13455	104	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	1	13383	13412	13412	5643	3342	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3210	1	19	2	2	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	0	13383	13412	13412	5553	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	1	13383	13412	13412	5538	3353	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3210	2	19	2	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	280	0	25	50100	40100	10000	40100	10000	587442	80000	0	13383	13412	13412	5538	3353	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3210	1	19	1	1	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	101	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	0	13383	13412	13412	6026	3353	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3210	1	19	2	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	66	0	25	50100	40100	10000	40100	10000	574746	80000	1	13383	13412	13412	5538	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3210	2	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	213	0	25	50100	40100	10000	40100	10000	587442	80000	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3210	1	19	1	2	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	45	0	25	50100	40100	10000	40100	10000	574746	80000	1	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	2	1	50201	100	99	100	40100	10000	100	0	0	3210	1	19	2	2	13409	40000	40100	13413	13413	13413	13413	13413
50204	13412	100	0	45	0	25	50100	40100	10000	40100	10000	587442	80000	0	13383	13412	13412	6026	3081	3	7117	50100	40200	10000	120200	20000	13412	13412	1	1	50201	100	99	100	40100	10000	100	0	0	3210	1	19	1	1	13408	40000	40100	13413	13413	13413	13413	13413

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3346

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	flags prf full (73)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
50024	13404	100	0	710	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	4	17	19	8	4	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	4	6	19	6	4	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	101	0	459	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	4	3	19	3	7	13379	40000	40010	13383	13383	13383	13558	13383
50024	13382	100	0	45	44	50107	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13429	1	1	50021	10	9	10	40010	10000	10	0	3140	4	5	19	4	6	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	4	3	19	6	5	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	3	4	19	5	3	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	1	13353	13382	13382	5951	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	4	5	19	5	5	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3254	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	1	3140	4	4	19	8	1	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	108	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5580	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	1	1	50021	10	9	10	40010	10000	10	0	3140	3	3	19	4	7	13379	40000	40010	13383	13383	13383	13383	13383
50024	13382	100	0	45	25	50010	40010	10000	40010	10000	573456	80000	0	13353	13382	13382	5951	3913	3	7109	50010	40020	10000	120020	20000	13382	13382	2	1	50021	10	9	10	40010	10000	10	0	3140	3	4	19	4	6	13379	40000	40010	13383	13383	13383	13383	13383

ADCS (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: Latency 4->4

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 9: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations