Apple Microarchitecture Research by Dougall Johnson
M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Icestorm Base Instructions
LAT : latency in cycles (cycles per instruction when latency bound)
TP : reciprocal throughput (cycles per instruction when throughput bound)
Uops : uop count (towards the pipeline width limit)
Int /Mem /FP : issue counts for each group of units (towards the one per unit per cycle limit)
Units : best guess of units used
LAT TP Uops Int Mem FP Units ADD (extend) 2 0.667 1 2 - - 2*u1-3
ADD (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADD (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADD (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADD (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADD (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADD (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADD (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADD (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADD (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADD (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADD 1 0.333 1 1 - - u1-3
ADD (uxtw, 32-bit) 1 0.333 1 1 - - u1-3
ADD (sxtw, 32-bit) 1 0.333 1 1 - - u1-3
ADD (uxtx, 64-bit) 1 0.333 1 1 - - u1-3
ADD (sxtx, 64-bit) 1 0.333 1 1 - - u1-3
ADD (immediate, 32-bit) 1 0.333 1 1 - - u1-3
ADD (immediate, 64-bit) 1 0.333 1 1 - - u1-3
ADD (shifted immediate, 32-bit) 1 0.333 1 1 - - u1-3
ADD (shifted immediate, 64-bit) 1 0.333 1 1 - - u1-3
ADD (register, 32-bit) 1 0.333 1 1 - - u1-3
ADD (register, 64-bit) 1 0.333 1 1 - - u1-3
ADD (shift) 2 0.667 1 2 - - 2*u1-3
ADD (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADD (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADD (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADD (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADD (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADD (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (extend) 2 0.667 1 2 - - 2*u1-3
ADDS (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS 1 0.5 1 1 - - u1-3
ADDS (uxtw, 32-bit) 1 0.5 1 1 - - u1-3
ADDS (sxtw, 32-bit) 1 0.5 1 1 - - u1-3
ADDS (uxtx, 64-bit) 1 0.5 1 1 - - u1-3
ADDS (sxtx, 64-bit) 1 0.5 1 1 - - u1-3
ADDS (immediate, 32-bit) 1 0.5 1 1 - - u1-3
ADDS (immediate, 64-bit) 1 0.5 1 1 - - u1-3
ADDS (shifted immediate, 32-bit) 1 0.5 1 1 - - u1-3
ADDS (shifted immediate, 64-bit) 1 0.5 1 1 - - u1-3
ADDS (register, 32-bit) 1 0.5 1 1 - - u1-3
ADDS (register, 64-bit) 1 0.5 1 1 - - u1-3
ADDS (shift) 2 0.667 1 2 - - 2*u1-3
ADDS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADR 0.25 1 0.5 - - - ADRP 0.25 1 0.5 - - - AND (shift) 2 0.667 1 2 - - 2*u1-3
AND (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
AND (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
AND (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
AND (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
AND (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
AND (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
AND (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
AND (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (shift) 2 0.667 1 2 - - 2*u1-3
ANDS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
AXFLAG 1 0.556 1 1 - - u1-3 B 1.049 1 - - - - B.cc (not taken) 0.584 1 1 - - u1-3 B.cc (taken) 1.154 1 1 - - u1-3 BIC (shift) 2 0.667 1 2 - - 2*u1-3
BIC (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
BIC (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
BIC (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
BIC (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
BIC (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
BIC (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
BIC (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
BIC (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
BICS (shift) 2 0.667 1 2 - - 2*u1-3
BICS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
BL 1.049 1 - - - - CASB 7 4 - 3 - CASAB 7 4 - 3 - CASALB 9 4 - 3 - CASLB 9 4 - 3 - CASH 7 4 - 3 - CASAH 7 4 - 3 - CASALH 9 4 - 3 - CASLH 9 4 - 3 - CASP (32-bit) 17 6 - 3 - CASP (64-bit) 17 6 - 3.04 - CBNZ (not taken) 0.584 1 1 - - u1-3 CBNZ (taken) 1.062 1 1 - - u1-3 CBZ (not taken) 0.584 1 1 - - u1-3 CBZ (taken) 1.062 1 1 - - u1-3 CFINV 1 0.556 1 1 - - u1-3 CLREX 4.996 1 - 1 - CMN (extend) 2 0.667 1 2 - - 2*u1-3
CMN (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN 1 0.363 1 1 - - u1-3
CMN (uxtw, 32-bit) 1 0.363 1 1 - - u1-3
CMN (sxtw, 32-bit) 1 0.363 1 1 - - u1-3
CMN (uxtx, 64-bit) 1 0.363 1 1 - - u1-3
CMN (sxtx, 64-bit) 1 0.363 1 1 - - u1-3
CMN (immediate, 32-bit) 1 0.363 1 1 - - u1-3
CMN (immediate, 64-bit) 1 0.363 1 1 - - u1-3
CMN (shifted immediate, 32-bit) 1 0.363 1 1 - - u1-3
CMN (shifted immediate, 64-bit) 1 0.363 1 1 - - u1-3
CMN (register, 32-bit) 1 0.363 1 1 - - u1-3
CMN (register, 64-bit) 1 0.363 1 1 - - u1-3
CMN (shift) 2 0.667 1 2 - - 2*u1-3
CMN (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (extend) 2 0.667 1 2 - - 2*u1-3
CMP (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxtw, 32-bit) 1 0.363 1 1 - - u1-3 CMP (sxtw, 32-bit) 1 0.363 1 1 - - u1-3 CMP (uxtx, 64-bit) 1 0.362 1 1 - - u1-3 CMP (sxtx, 64-bit) 1 0.363 1 1 - - u1-3 CMP (immediate, 32-bit) 1 0.363 1 1 - - u1-3 CMP (immediate, 64-bit) 1 0.363 1 1 - - u1-3 CMP (shifted immediate, 32-bit) 1 0.362 1 1 - - u1-3 CMP (shifted immediate, 64-bit) 1 0.363 1 1 - - u1-3 CMP (register, 32-bit) 1 0.363 1 1 - - u1-3 CMP (register, 64-bit) 1 0.362 1 1 - - u1-3 CMP (shift) 2 0.667 1 2 - - 2*u1-3
CMP (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
CSDB 0.254 1 - - - - EON (shift) 2 0.667 1 2 - - 2*u1-3
EON (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
EON (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
EON (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
EON (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
EON (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
EON (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
EON (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
EON (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
EOR (shift) 2 0.667 1 2 - - 2*u1-3
EOR (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
EOR (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
EOR (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
EOR (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
EOR (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
EOR (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
EOR (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
EOR (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
ISB (SY) 25 4 - - - - LDP (post-index, 32-bit) 0.75 3 1 1 - LDP (post-index, 64-bit) 0.763 3 1 1 - LDP (pre-index, 32-bit) 0.75 3 1 1 - LDP (pre-index, 64-bit) 0.763 3 1 1 - LDPSW (post-index) 0.75 3 1 1 - LDPSW (pre-index) 0.75 3 1 1 - LDPSW (signed offset) ≤4 0.5 2 - 1 - u4/5 LDR (register) ≤4 0.5 1 - 1 - u4/5
LDR (register, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDR (register, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDR (register, uxtw, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDR (register, uxtw, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDR (register, sxtw, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDR (register, sxtw, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDR (register, lsl, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDR (register, lsl, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDRB ≤4 0.5 1 - 1 - u4/5 LDRB (post-index) 0.54 2 1 1 - LDRB (pre-index) 0.54 2 1 1 - LDRB (unsigned offset) ≤4 0.5 1 - 1 - u4/5 LDRH ≤4 0.5 1 - 1 - u4/5 LDRH (post-index) 0.54 2 1 1 - LDRH (pre-index) 0.54 2 1 1 - LDRH (unsigned offset) ≤4 0.5 1 - 1 - u4/5 LDRSB (register) ≤4 0.5 1 - 1 - u4/5
LDRSB (register, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDRSB (register, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDRSB (register, uxtw, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDRSB (register, uxtw, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDRSB (register, sxtw, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDRSB (register, sxtw, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDRSH (post-index, 32-bit) 0.541 2 1 1 - LDRSH (post-index, 64-bit) 0.54 2 1 1 - LDRSH (register) ≤4 0.5 1 - 1 - u4/5
LDRSH (register, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDRSH (register, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDRSH (register, uxtw, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDRSH (register, uxtw, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDRSH (register, sxtw, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDRSH (register, sxtw, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDRSH (register, lsl, 32-bit) ≤4 0.5 1 - 1 - u4/5
LDRSH (register, lsl, 64-bit) ≤4 0.5 1 - 1 - u4/5
LDRSW ≤4 0.5 1 - 1 - u4/5 LDRSW (post-index) 0.54 2 1 1 - LDRSW (pre-index) 0.54 2 1 1 - LDRSW (unsigned offset) ≤4 0.5 1 - 1 - u4/5 LDRSW (literal) 0.5 1 - 1 - u4/5 LDURB 0.5 1 - 1 - u4/5 LDURH 0.5 1 - 1 - u4/5 LDURSW 0.5 1 - 1 - u4/5 MOV (bitmask immediate, 32-bit) 0.25 1 - - - - MOV (bitmask immediate, 64-bit) 0.25 1 - - - - MOV (from sp, 32-bit) 0.333 1 1 - - u1-3 MOV (from sp, 64-bit) 0.25 1 0.5 - - - MRS (CNTFRQ_EL0) 16 1 1 - - MRS (CNTPCT_EL0) 1.25 1 1 - - MRS (CNTVCT_EL0) 1.25 1 1 - - MRS (DCZID_EL0) 1.25 1 1 - - MRS (FPCR) 1.25 1 1 - - MRS (FPSR) 7 1 1 - - MRS (NZCV) 0.333 1 1 - - u1-3 MRS (TPIDRRO_EL0) 1.25 1 1 - - MRS (TPIDR_EL0) 1.25 1 1 - - MRS (DIT) 1.25 1 1 - - MRS (SSBS) 1.25 1 1 - - MRS (APRR) 1.25 1 1 - - MSR (DIT) 1 1 1 - - MSR (SSBS) 27 4 1 - - MSR (APRR) 1.26 1 1 - - MSR (FPCR) 1 1 1 - - MSR (FPSR) 1 1 1 - - MSR (TPIDR_EL0) 1 1 1 - - MSR (NZCV) 0.366 1 1 - - u1-3 MVN (shift) 2 0.667 1 2 - - 2*u1-3
MVN (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
MVN (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
MVN (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
MVN (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
MVN (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
MVN (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
MVN (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
MVN (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
NEG (shift) 2 0.667 1 2 - - 2*u1-3
NEG (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
NEG (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
NEG (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
NEG (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
NEG (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
NEG (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (shift) 2 0.667 1 2 - - 2*u1-3
NEGS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
NOP 0.25 1 - - - - ORN (shift) 2 0.667 1 2 - - 2*u1-3
ORN (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
ORN (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
ORN (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ORN (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ORN (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ORN (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ORN (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
ORN (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
ORR (shift) 2 0.667 1 2 - - 2*u1-3
ORR (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
ORR (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
ORR (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ORR (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ORR (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ORR (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ORR (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
ORR (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
PRFM (register, PLDL1KEEP) 2 1 - 1 - PRFM (register, PLDL1STRM) 1.996 1 - 1 - PRFM (register, PLDL2KEEP) 1.872 1 - 1 - PRFM (register, PLDL2STRM) 1.872 1 - 1 - PRFM (register, PLDL3KEEP) 2 1 - 1 - PRFM (register, PLDL3STRM) 2 1 - 1 - PRFM (register, PLIL1KEEP) 2 1 - 1 - PRFM (register, PLIL1STRM) 1.962 1 - 1 - PRFM (register, PLIL2KEEP) 2 1 - 1 - PRFM (register, PLIL2STRM) 2 1 - 1 - PRFM (register, PLIL3KEEP) 1.999 1 - 1 - PRFM (register, PLIL3STRM) 2 1 - 1 - PRFM (register, PSTL1KEEP) 1.872 1 - 1 - PRFM (register, PSTL1STRM) 1.973 1 - 1 - PRFM (register, PSTL2KEEP) 2 1 - 1 - PRFM (register, PSTL2STRM) 1.872 1 - 1 - PRFM (register, PSTL3KEEP) 2 1 - 1 - PRFM (register, PSTL3STRM) 1.873 1 - 1 - PSSBB 22 4 - 1 - REV32 1 0.333 1 1 - - u1-3 RMIF 1 0.556 1 1 - - u1-3 SB 22 4 - 1 - SDIV (fast, 32-bit) 7 7 1 2 - - u2 SDIV (slow, 32-bit) 13 13 1 2 - - u2 SDIV (slow, 32-bit) 13 13 1 2 - - u2 SDIV (fast, 64-bit) 7 7 1 2 - - u2 SDIV (medium, 64-bit) 13 13 1 2 - - u2 SDIV (medium, 64-bit) 13 13 1 2 - - u2 SDIV (slow, 64-bit) 21 21 1 2 - - u2 SDIV (slow, 64-bit) 21 21 1 2 - - u2 SETF8 1 0.556 1 1 - - u1-3 SETF16 1 0.556 1 1 - - u1-3 SMADDL [1;3] 1 1 1 - - u3 SMNEGL 3 1 1 1 - - u3 SMSUBL [1;3] 1 1 1 - - u3 SMULH 3 1 1 1 - - u3 SMULL 3 1 1 1 - - u3 SSBB 22 4 - 1 - STADDB 3 3 1 2 - STADDLB 6 3 1 2 - STADDH 3 3 1 2 - STADDLH 6 3 1 2 - STCLRB 3 3 1 2 - STCLRLB 6 3 1 2 - STCLRH 3 3 1 2 - STCLRLH 6 3 1 2 - STEORB 3 3 1 2 - STEORLB 6 3 1 2 - STEORH 3 3 1 2 - STEORLH 6 3 1 2 - STLLRB 6 1 - 1 - STLLRH 6 1 - 1 - STLRB 6 1 - 1 - STLRH 6 1 - 1 - STLXRB 3 1 - 1 - STLXRH 3 1 - 1 - STP (post-index, 32-bit) 1 1 1 1 - STP (post-index, 64-bit) 1.014 1 1 1 - STP (pre-index, 32-bit) 1 1 1 1 - STP (pre-index, 64-bit) 1.014 1 1 1 - STR (register) 1 1 - 1 - u4
STR (register, 32-bit) 1 1 - 1 - u4
STR (register, 64-bit) 1 1 - 1 - u4
STR (register, uxtw, 32-bit) 1 1 - 1 - u4
STR (register, uxtw, 64-bit) 1 1 - 1 - u4
STR (register, sxtw, 32-bit) 1 1 - 1 - u4
STR (register, sxtw, 64-bit) 1 1 - 1 - u4
STR (register, lsl, 32-bit) 1 1 - 1 - u4
STR (register, lsl, 64-bit) 1 1 - 1 - u4
STRB 1 1 - 1 - u4 STRB (post-index) 1 1 1 1 - STRB (pre-index) 1 1 1 1 - STRB (unsigned offset) 1 1 - 1 - u4 STRH 1 1 - 1 - u4 STRH (post-index) 1 1 1 1 - STRH (pre-index) 1 1 1 1 - STRH (unsigned offset) 1 1 - 1 - u4 STURB 1 1 - 1 - u4 STURH 1 1 - 1 - u4 STXP (64-bit) 2.509 1 - 1 - STXR (32-bit) 2.186 1 - 1 - STXR (64-bit) 2.34 1 - 1 - STXRB 2.107 1 - 1 - STXRH 2.107 1 - 1 - SUB (extend) 2 0.667 1 2 - - 2*u1-3
SUB (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUB (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUB (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUB (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUB (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUB (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUB (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUB (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUB (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUB (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUB 1 0.333 1 1 - - u1-3
SUB (uxtw, 32-bit) 1 0.333 1 1 - - u1-3
SUB (sxtw, 32-bit) 1 0.333 1 1 - - u1-3
SUB (uxtx, 64-bit) 1 0.333 1 1 - - u1-3
SUB (sxtx, 64-bit) 1 0.333 1 1 - - u1-3
SUB (immediate, 32-bit) 1 0.333 1 1 - - u1-3
SUB (immediate, 64-bit) 1 0.333 1 1 - - u1-3
SUB (shifted immediate, 32-bit) 1 0.333 1 1 - - u1-3
SUB (shifted immediate, 64-bit) 1 0.333 1 1 - - u1-3
SUB (register, 32-bit) 1 0.333 1 1 - - u1-3
SUB (register, 64-bit) 1 0.333 1 1 - - u1-3
SUB (shift) 2 0.667 1 2 - - 2*u1-3
SUB (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUB (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUB (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUB (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUB (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUB (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (extend) 2 0.667 1 2 - - 2*u1-3
SUBS (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS 1 0.5 1 1 - - u1-3
SUBS (uxtw, 32-bit) 1 0.5 1 1 - - u1-3
SUBS (sxtw, 32-bit) 1 0.5 1 1 - - u1-3
SUBS (uxtx, 64-bit) 1 0.5 1 1 - - u1-3
SUBS (sxtx, 64-bit) 1 0.5 1 1 - - u1-3
SUBS (immediate, 32-bit) 1 0.5 1 1 - - u1-3
SUBS (immediate, 64-bit) 1 0.5 1 1 - - u1-3
SUBS (shifted immediate, 32-bit) 1 0.5 1 1 - - u1-3
SUBS (shifted immediate, 64-bit) 1 0.5 1 1 - - u1-3
SUBS (register, 32-bit) 1 0.5 1 1 - - u1-3
SUBS (register, 64-bit) 1 0.5 1 1 - - u1-3
SUBS (shift) 2 0.667 1 2 - - 2*u1-3
SUBS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
SWPB 3 2 - 2 - SWPAB 6 2 - 2 - SWPALB 6 2 - 2 - SWPLB 6 2 - 2 - SWPH 3 2 - 2 - SWPAH 6 2 - 2 - SWPALH 6 2 - 2 - SWPLH 6 2 - 2 - SXTW 1 0.333 1 1 - - u1-3 TBNZ (not taken) 0.584 1 1 - - u1-3 TBNZ (taken) 1.062 1 1 - - u1-3 TBZ (not taken) 0.584 1 1 - - u1-3 TBZ (taken) 1.061 1 1 - - u1-3 TST (shift) 2 0.667 1 2 - - 2*u1-3
TST (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
TST (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
TST (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
TST (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
TST (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
TST (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
UDIV (fast, 32-bit) 7 7 1 2 - - u2 UDIV (slow, 32-bit) 13 13 1 2 - - u2 UDIV (fast, 64-bit) 7 7 1 2 - - u2 UDIV (medium, 64-bit) 13 13 1 2 - - u2 UDIV (slow, 64-bit) 21 21 1 2 - - u2 UMADDL [1;3] 1 1 1 - - u3 UMNEGL 3 1 1 1 - - u3 UMSUBL [1;3] 1 1 1 - - u3 UMULH 3 1 1 1 - - u3 UMULL 3 1 1 1 - - u3 UXTB 1 0.333 1 1 - - u1-3 UXTH 1 0.333 1 1 - - u1-3 XAFLAG 1 0.555 1 1 - - YIELD 0.254 1 - - - -