Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRSH (register, uxtw, 32-bit)

Test 1: uops

Code:

  ldrsh w0, [x6, w7, uxtw]
  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056581029110281000816610001000200011000
10045501001110001000822010001000200011000
10045581001110001000816610001000200011000
10045501001110001000820210001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000
10045521001110001000816610001000200011000
10045501001110001000816610001000200011000
10045501001110001000816610001000200011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
402057015040108301071000130130100031859587693941040106302101000406022020008300031000030100
402047004940103301031000030103100031859635694083040106302121000406022420008300031000030100
402047004940103301031000030103100151859980694200040150302511001706022420008300031000030100
402047004940103301031000030103100031859635694083040106302121000406022420008300031000030100
402047005740103301031000030103100031859635694083040106302121000406030220036300101000030100
402047005540103301031000030103100031859635694083040106302121000406022420008300031000030100
402047005340103301031000030103100031859635694083040106302121000406022420008300031000030100
402047004940103301031000030103100031859635694083040106302121000406022420008300031000030100
402047004940103301031000030103100031859635694083040106302121000406022420008300031000030100
402047004940103301031000030103100031859635694083040106302121000406022420008300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570155400183001710001300401000018596106936294001030020100006012220034300091000030010
4002470049400133001310000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010
4002470105400133001310000300101000018600576948844001030020100006002020000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002020000300021000030010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570156401083010710001301301000318595876939414010630210100046022020008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046030220034300091000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570150400183001710001300401000318596776937164001630030100046002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470052400133001310000300101000018597066947344001030020100006002020000300031000030010
4002570177400223002010002300451001518628607072444006030068100176004420008300041000030010
4002470051400133001310000300101000018597066947364001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006011420034300111000030010
4002470050400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470049400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010

Test 4: throughput

Count: 8

Code:

  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205401718012910180028100800083002481908010820080012200160024180000100
80204400598010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204401338010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400568010110180000100800083006402868010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025402078003511800241080010306401548002020800142016002418000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016000018000010
80024400478001111800001080000306401128001020800002016014218000010