Icestorm: LDRSH (register, uxtw, 32-bit) measurements

Code:

  ldrsh w0, [x6, w7, uxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	658	1029	1	1028	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8220	1000	1000	2000	1	1000
1004	558	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8202	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	552	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8166	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70150	40108	30107	10001	30130	10003	1859587	693941	0	40106	30210	10004	0	60220	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10015	1859980	694200	0	40150	30251	10017	0	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	20008	30003	10000	30100
40204	70057	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60302	20036	30010	10000	30100
40204	70055	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	20008	30003	10000	30100
40204	70053	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	0	40106	30212	10004	0	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70155	40018	30017	10001	30040	10000	1859610	693629	40010	30020	10000	60122	20034	30009	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70105	40013	30013	10000	30010	10000	1860057	694884	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70156	40108	30107	10001	30130	10003	1859587	693941	40106	30210	10004	60220	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60302	20034	30009	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70150	40018	30017	10001	30040	10003	1859677	693716	40016	30030	10004	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70052	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40025	70177	40022	30020	10002	30045	10015	1862860	707244	40060	30068	10017	60044	20008	30004	10000	30010
40024	70051	40013	30013	10000	30010	10000	1859706	694736	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60114	20034	30011	10000	30010
40024	70050	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	20000	30003	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]
  ldrsh w0, [x6, w7, uxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40171	80129	101	80028	100	80008	300	248190	80108	200	80012	200	160024	1	80000	100
80204	40059	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40133	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640286	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40207	80035	11	80024	10	80010	30	640154	80020	20	80014	20	160024	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	160142	1	80000	10

LDRSH (register, uxtw, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations