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Apple Microarchitecture Research by Dougall Johnson
M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Firestorm Base Instructions
LAT : latency in cycles (cycles per instruction when latency bound)
TP : reciprocal throughput (cycles per instruction when throughput bound)
Uops : uop count (towards the pipeline width limit)
Int /Mem /FP : issue counts for each group of units (towards the one per unit per cycle limit)
Units : best guess of units used
LAT TP Uops Int Mem FP Units ADD (extend) 2 0.333 1 2 - - 2*u1-6
ADD (sxtb, 32-bit) 2 0.333 1 2 - - 2*u1-6
ADD (sxtb, 64-bit) 2 0.333 1 2 - - 2*u1-6
ADD (uxtb, 32-bit) 2 0.333 1 2 - - 2*u1-6
ADD (uxtb, 64-bit) 2 0.333 1 2 - - 2*u1-6
ADD (sxth, 32-bit) 2 0.333 1 2 - - 2*u1-6
ADD (sxth, 64-bit) 2 0.333 1 2 - - 2*u1-6
ADD (uxth, 32-bit) 2 0.333 1 2 - - 2*u1-6
ADD (uxth, 64-bit) 2 0.333 1 2 - - 2*u1-6
ADD (sxtw, 64-bit) 2 0.333 1 2 - - 2*u1-6
ADD (uxtw, 64-bit) 2 0.333 1 2 - - 2*u1-6
ADD 1 0.167 1 1 - - u1-6
ADD (uxtw, 32-bit) 1 0.167 1 1 - - u1-6
ADD (sxtw, 32-bit) 1 0.167 1 1 - - u1-6
ADD (uxtx, 64-bit) 1 0.167 1 1 - - u1-6
ADD (sxtx, 64-bit) 1 0.167 1 1 - - u1-6
ADD (immediate, 32-bit) 1 0.167 1 1 - - u1-6
ADD (immediate, 64-bit) 1 0.167 1 1 - - u1-6
ADD (shifted immediate, 32-bit) 1 0.167 1 1 - - u1-6
ADD (shifted immediate, 64-bit) 1 0.167 1 1 - - u1-6
ADD (register, 32-bit) 1 0.167 1 1 - - u1-6
ADD (register, 64-bit) 1 0.167 1 1 - - u1-6
ADD (shift) 2 0.333 1 2 - - 2*u1-6
ADD (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6
ADD (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6
ADD (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6
ADD (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6
ADD (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6
ADD (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6
ADDS (extend) 2 0.667 1 2 - - 2*u1-3
ADDS (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS 1 0.333 1 1 - - u1-3
ADDS (uxtw, 32-bit) 1 0.333 1 1 - - u1-3
ADDS (sxtw, 32-bit) 1 0.333 1 1 - - u1-3
ADDS (uxtx, 64-bit) 1 0.333 1 1 - - u1-3
ADDS (sxtx, 64-bit) 1 0.333 1 1 - - u1-3
ADDS (immediate, 32-bit) 1 0.333 1 1 - - u1-3
ADDS (immediate, 64-bit) 1 0.333 1 1 - - u1-3
ADDS (shifted immediate, 32-bit) 1 0.333 1 1 - - u1-3
ADDS (shifted immediate, 64-bit) 1 0.333 1 1 - - u1-3
ADDS (register, 32-bit) 1 0.333 1 1 - - u1-3
ADDS (register, 64-bit) 1 0.333 1 1 - - u1-3
ADDS (shift) 2 0.667 1 2 - - 2*u1-3
ADDS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ADDS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ADR 0.5 1 1 - - u1/2 ADRP 0.5 1 1 - - u1/2 AND (shift) 2 0.333 1 2 - - 2*u1-6
AND (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6
AND (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6
AND (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6
AND (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6
AND (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6
AND (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6
AND (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6
AND (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6
ANDS (shift) 2 0.667 1 2 - - 2*u1-3
ANDS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
ANDS (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
AXFLAG 1 0.333 1 1 - - u1-3 B 1 1 - - - - B.cc (not taken) 0.5 1 1 - - u1/2 B.cc (taken) 1 1 1 - - u1/2 BIC (shift) 2 0.333 1 2 - - 2*u1-6
BIC (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6
BIC (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6
BIC (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6
BIC (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6
BIC (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6
BIC (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6
BIC (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6
BIC (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6
BICS (shift) 2 0.667 1 2 - - 2*u1-3
BICS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, ror, 32-bit) 2 0.667 1 2 - - 2*u1-3
BICS (register, ror, 64-bit) 2 0.667 1 2 - - 2*u1-3
BL 1 1 1 - - u1/2 CASA (32-bit) 3 4 - 3 - CASA (64-bit) 3.053 4 - 3 - CASB 3 4 - 3 - CASAB 3 4 - 3 - CASALB 7 4 - 3 - CASLB 7 4 - 3 - CASH 3 4 - 3 - CASAH 3 4 - 3 - CASALH 7 4 - 3 - CASLH 7 4 - 3 - CBNZ (not taken) 0.5 1 1 - - u1/2 CBNZ (taken) 1.01 1 1 - - u1/2 CBZ (not taken) 0.5 1 1 - - u1/2 CBZ (taken) 1 1 1 - - u1/2 CFINV 1 0.333 1 1 - - u1-3 CLREX 4.976 1 - 1 - CMN (extend) 2 0.667 1 2 - - 2*u1-3
CMN (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN 1 0.333 1 1 - - u1-3
CMN (uxtw, 32-bit) 1 0.333 1 1 - - u1-3
CMN (sxtw, 32-bit) 1 0.333 1 1 - - u1-3
CMN (uxtx, 64-bit) 1 0.333 1 1 - - u1-3
CMN (sxtx, 64-bit) 1 0.333 1 1 - - u1-3
CMN (immediate, 32-bit) 1 0.333 1 1 - - u1-3
CMN (immediate, 64-bit) 1 0.333 1 1 - - u1-3
CMN (shifted immediate, 32-bit) 1 0.333 1 1 - - u1-3
CMN (shifted immediate, 64-bit) 1 0.333 1 1 - - u1-3
CMN (register, 32-bit) 1 0.333 1 1 - - u1-3
CMN (register, 64-bit) 1 0.333 1 1 - - u1-3
CMN (shift) 2 0.667 1 2 - - 2*u1-3
CMN (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMN (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMN (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (extend) 2 0.667 1 2 - - 2*u1-3
CMP (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP 1 0.333 1 1 - - u1-3
CMP (uxtw, 32-bit) 1 0.333 1 1 - - u1-3
CMP (sxtw, 32-bit) 1 0.333 1 1 - - u1-3
CMP (uxtx, 64-bit) 1 0.333 1 1 - - u1-3
CMP (sxtx, 64-bit) 1 0.333 1 1 - - u1-3
CMP (immediate, 32-bit) 1 0.333 1 1 - - u1-3
CMP (immediate, 64-bit) 1 0.333 1 1 - - u1-3
CMP (shifted immediate, 32-bit) 1 0.333 1 1 - - u1-3
CMP (shifted immediate, 64-bit) 1 0.333 1 1 - - u1-3
CMP (register, 32-bit) 1 0.333 1 1 - - u1-3
CMP (register, 64-bit) 1 0.333 1 1 - - u1-3
CMP (shift) 2 0.667 1 2 - - 2*u1-3
CMP (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
CMP (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
CMP (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
CSDB 27 4 - 1 - DMB (SY) 2.913 1 - 1 - DMB (ST) 2.904 1 - 1 - DMB (LD) 2.904 1 - 1 - DMB (ISH) 2.913 1 - 1 - DMB (ISHST) 2.913 1 - 1 - DMB (ISHLD) 2.904 1 - 1 - DMB (NSH) 2.904 1 - 1 - DMB (NSHST) 2.904 1 - 1 - DMB (NSHLD) 2.904 1 - 1 - DMB (OSH) 2.904 1 - 1 - DMB (OSHST) 2.913 1 - 1 - DMB (OSHLD) 2.904 1 - 1 - EON (shift) 2 0.333 1 2 - - 2*u1-6
EON (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6
EON (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6
EON (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6
EON (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6
EON (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6
EON (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6
EON (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6
EON (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6
EOR (shift) 2 0.333 1 2 - - 2*u1-6
EOR (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6
EOR (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6
EOR (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6
EOR (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6
EOR (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6
EOR (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6
EOR (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6
EOR (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6
ISB (SY) 28 4 - - - - LDP (post-index, 32-bit) 0.396 3 1 1 - LDP (post-index, 64-bit) 0.407 3 1 1 - LDP (pre-index, 32-bit) 0.394 3 1 1 - LDP (pre-index, 64-bit) 0.406 3 1 1 - LDPSW (post-index) 0.393 3 1 1 - LDPSW (pre-index) 0.396 3 1 1 - LDPSW (signed offset) ≤4 0.333 2 - 1 - u8-10 LDR (pre-index, 32-bit) 0.366 2 1 1 - LDR (pre-index, 64-bit) 0.368 2 1 1 - LDR (register) ≤4 0.333 1 - 1 - u8-10
LDR (register, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDR (register, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDR (register, uxtw, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDR (register, uxtw, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDR (register, sxtw, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDR (register, sxtw, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDR (register, lsl, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDR (register, lsl, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDRB ≤4 0.333 1 - 1 - u8-10 LDRB (post-index) 0.364 2 1 1 - LDRB (pre-index) 0.365 2 1 1 - LDRB (unsigned offset) ≤4 0.333 1 - 1 - u8-10 LDRH ≤4 0.333 1 - 1 - u8-10 LDRH (post-index) 0.368 2 1 1 - LDRH (pre-index) 0.366 2 1 1 - LDRH (unsigned offset) ≤4 0.333 1 - 1 - u8-10 LDRSB (post-index, 32-bit) 0.364 2 1 1 - LDRSB (post-index, 64-bit) 0.365 2 1 1 - LDRSB (pre-index, 32-bit) 0.365 2 1 1 - LDRSB (pre-index, 64-bit) 0.364 2 1 1 - LDRSB (register) ≤4 0.333 1 - 1 - u8-10
LDRSB (register, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDRSB (register, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDRSB (register, uxtw, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDRSB (register, uxtw, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDRSB (register, sxtw, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDRSB (register, sxtw, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDRSH (post-index, 32-bit) 0.368 2 1 1 - LDRSH (post-index, 64-bit) 0.365 2 1 1 - LDRSH (pre-index, 32-bit) 0.364 2 1 1 - LDRSH (pre-index, 64-bit) 0.367 2 1 1 - LDRSH (register) ≤4 0.333 1 - 1 - u8-10
LDRSH (register, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDRSH (register, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDRSH (register, uxtw, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDRSH (register, uxtw, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDRSH (register, sxtw, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDRSH (register, sxtw, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDRSH (register, lsl, 32-bit) ≤4 0.333 1 - 1 - u8-10
LDRSH (register, lsl, 64-bit) ≤4 0.333 1 - 1 - u8-10
LDRSW ≤4 0.333 1 - 1 - u8-10 LDRSW (post-index) 0.367 2 1 1 - LDRSW (pre-index) 0.366 2 1 1 - LDRSW (unsigned offset) ≤4 0.333 1 - 1 - u8-10 LDRSW (literal) 0.333 1 - 1 - u8-10 LDURB 0.333 1 - 1 - u8-10 LDURH 0.333 1 - 1 - u8-10 LDURSW 0.333 1 - 1 - u8-10 MOV (bitmask immediate, 32-bit) 0.125 1 - - - - MOV (bitmask immediate, 64-bit) 0.125 1 - - - - MOV (from sp, 32-bit) 0.167 1 1 - - u1-6 MOV (from sp, 64-bit) 0.125 1 - - - - MRS (CNTFRQ_EL0) 8.501 1 1 - - MRS (CNTPCT_EL0) 1 1 1 - - u1 MRS (CNTVCT_EL0) 1 1 1 - - u1 MRS (DCZID_EL0) 1 1 1 - - u1 MRS (FPCR) 1 1 1 - - u1 MRS (FPSR) 1 1 1 - - u1 MRS (NZCV) 0.5 1 1 - - u1/2 MRS (TPIDRRO_EL0) 1 1 1 - - u1 MRS (TPIDR_EL0) 1 1 1 - - u1 MRS (DIT) 1 1 1 - - u1 MRS (SSBS) 1 1 1 - - u1 MRS (APRR) 1 1 1 - - u1 MSR (DIT) 12 1 - - - - MSR (SSBS) 3 4 - - - - MSR (APRR) 1.014 1 - - - - MSR (FPCR) 11 1 - - - - MSR (FPSR) 12 1 - - - - MSR (TPIDR_EL0) 12 1 - - - - MSR (NZCV) 0.5 1 1 - - u1/2 MVN (shift) 2 0.333 1 2 - - 2*u1-6
MVN (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6
MVN (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6
MVN (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6
MVN (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6
MVN (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6
MVN (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6
MVN (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6
MVN (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6
NEG (shift) 2 0.333 1 2 - - 2*u1-6
NEG (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6
NEG (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6
NEG (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6
NEG (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6
NEG (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6
NEG (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6
NEGS (shift) 2 0.667 1 2 - - 2*u1-3
NEGS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
NEGS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
NOP 0.125 1 - - - - ORN (shift) 2 0.333 1 2 - - 2*u1-6
ORN (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6
ORN (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6
ORN (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6
ORN (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6
ORN (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6
ORN (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6
ORN (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6
ORN (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6
ORR (shift) 2 0.333 1 2 - - 2*u1-6
ORR (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6
ORR (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6
ORR (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6
ORR (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6
ORR (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6
ORR (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6
ORR (register, ror, 32-bit) 2 0.333 1 2 - - 2*u1-6
ORR (register, ror, 64-bit) 2 0.333 1 2 - - 2*u1-6
PRFM (register, PLDL1KEEP) 1.542 1 - 1 - PRFM (register, PLDL1STRM) 1.548 1 - 1 - PRFM (register, PLDL2KEEP) 1.543 1 - 1 - PRFM (register, PLDL2STRM) 1.403 1 - 1 - PRFM (register, PLDL3KEEP) 1.542 1 - 1 - PRFM (register, PLDL3STRM) 1.545 1 - 1 - PRFM (register, PLIL1KEEP) 1.542 1 - 1 - PRFM (register, PLIL1STRM) 1.353 1 - 1 - PRFM (register, PLIL2KEEP) 1.546 1 - 1 - PRFM (register, PLIL2STRM) 1.544 1 - 1 - PRFM (register, PLIL3KEEP) 1.549 1 - 1 - PRFM (register, PLIL3STRM) 1.546 1 - 1 - PRFM (register, PSTL1KEEP) 1.549 1 - 1 - PRFM (register, PSTL1STRM) 1.553 1 - 1 - PRFM (register, PSTL2KEEP) 1.54 1 - 1 - PRFM (register, PSTL2STRM) 1.544 1 - 1 - PRFM (register, PSTL3KEEP) 1.538 1 - 1 - PRFM (register, PSTL3STRM) 1.539 1 - 1 - PSSBB 27 4 - 1 - REV32 1 0.167 1 1 - - u1-6 RMIF 1 0.333 1 1 - - u1-3 SB 27 4 - 1 - SDIV (fast, 32-bit) 7 2 1 1 - - u5 SDIV (slow, 32-bit) 8 2 1 1 - - u5 SDIV (slow, 32-bit) 8 2 1 1 - - u5 SDIV (fast, 64-bit) 7 2 1 1 - - u5 SDIV (medium, 64-bit) 8 2 1 1 - - u5 SDIV (medium, 64-bit) 8 2 1 1 - - u5 SDIV (slow, 64-bit) 9 2 1 1 - - u5 SDIV (slow, 64-bit) 9 2 1 1 - - u5 SETF8 1 0.333 1 1 - - u1-3 SETF16 1 0.333 1 1 - - u1-3 SMADDL [1;3] 1 1 1 - - u6 SMNEGL 3 0.5 1 1 - - u5/6 SMSUBL [1;3] 1 1 1 - - u6 SMULH 3 0.5 1 1 - - u5/6 SMULL 3 0.5 1 1 - - u5/6 SSBB 27 4 - 1 - STADDB 3 3 1 2 - STADDLB 7 3 1 2 - STADDH 3 3 1 2 - STADDLH 7 3 1 2 - STCLRB 3 3 1 2 - STCLRLB 7 3 1 2 - STCLRH 3 3 1 2 - STCLRLH 7 3 1 2 - STEORB 3 3 1 2 - STEORLB 7 3 1 2 - STEORH 3 3 1 2 - STEORLH 7 3 1 2 - STLLRB 1 1 - 1 - STLLRH 1 1 - 1 - STLRB 1 1 - 1 - STLRH 1 1 - 1 - STLXRB 38 1 - 50.67 - STLXRH 38 1 - 50.67 - STP (post-index, 32-bit) 0.51 1 1 1 - STP (post-index, 64-bit) 0.524 1 1 1 - STP (pre-index, 32-bit) 0.51 1 1 1 - STP (pre-index, 64-bit) 0.524 1 1 1 - STR (post-index, 32-bit) 0.5 1 1 1 - u7/8, u1-6? STR (post-index, 64-bit) 0.51 1 1 1 - STR (pre-index, 32-bit) 0.505 1 1 1 - STR (pre-index, 64-bit) 0.51 1 1 1 - STR (register) 0.5 1 - 1 - u7/8
STR (register, 32-bit) 0.5 1 - 1 - u7/8
STR (register, 64-bit) 0.5 1 - 1 - u7/8
STR (register, uxtw, 32-bit) 0.5 1 - 1 - u7/8
STR (register, uxtw, 64-bit) 0.5 1 - 1 - u7/8
STR (register, sxtw, 32-bit) 0.5 1 - 1 - u7/8
STR (register, sxtw, 64-bit) 0.5 1 - 1 - u7/8
STR (register, lsl, 32-bit) 0.5 1 - 1 - u7/8
STR (register, lsl, 64-bit) 0.5 1 - 1 - u7/8
STRB 0.5 1 - 1 - u7/8 STRB (post-index) 0.505 1 1 1 - STRB (pre-index) 0.509 1 1 1 - STRB (unsigned offset) 0.5 1 - 1 - u7/8 STRH 0.5 1 - 1 - u7/8 STRH (post-index) 0.51 1 1 1 - STRH (pre-index) 0.51 1 1 1 - STRH (unsigned offset) 0.5 1 - 1 - u7/8 STURB 0.5 1 - 1 - u7/8 STURH 0.5 1 - 1 - u7/8 STXP (64-bit) 38 1 - 2.96 - STXRB 38 1 - 2.97 - STXRH 38 1 - 2.95 - SUB (extend) 2 0.333 1 2 - - 2*u1-6
SUB (sxtb, 32-bit) 2 0.333 1 2 - - 2*u1-6
SUB (sxtb, 64-bit) 2 0.333 1 2 - - 2*u1-6
SUB (uxtb, 32-bit) 2 0.333 1 2 - - 2*u1-6
SUB (uxtb, 64-bit) 2 0.333 1 2 - - 2*u1-6
SUB (sxth, 32-bit) 2 0.333 1 2 - - 2*u1-6
SUB (sxth, 64-bit) 2 0.333 1 2 - - 2*u1-6
SUB (uxth, 32-bit) 2 0.333 1 2 - - 2*u1-6
SUB (uxth, 64-bit) 2 0.333 1 2 - - 2*u1-6
SUB (sxtw, 64-bit) 2 0.333 1 2 - - 2*u1-6
SUB (uxtw, 64-bit) 2 0.333 1 2 - - 2*u1-6
SUB 1 0.167 1 1 - - u1-6
SUB (uxtw, 32-bit) 1 0.167 1 1 - - u1-6
SUB (sxtw, 32-bit) 1 0.167 1 1 - - u1-6
SUB (uxtx, 64-bit) 1 0.167 1 1 - - u1-6
SUB (sxtx, 64-bit) 1 0.167 1 1 - - u1-6
SUB (immediate, 32-bit) 1 0.167 1 1 - - u1-6
SUB (immediate, 64-bit) 1 0.167 1 1 - - u1-6
SUB (shifted immediate, 32-bit) 1 0.167 1 1 - - u1-6
SUB (shifted immediate, 64-bit) 1 0.167 1 1 - - u1-6
SUB (register, 32-bit) 1 0.167 1 1 - - u1-6
SUB (register, 64-bit) 1 0.167 1 1 - - u1-6
SUB (shift) 2 0.333 1 2 - - 2*u1-6
SUB (register, lsl, 32-bit) 2 0.333 1 2 - - 2*u1-6
SUB (register, lsl, 64-bit) 2 0.333 1 2 - - 2*u1-6
SUB (register, lsr, 32-bit) 2 0.333 1 2 - - 2*u1-6
SUB (register, lsr, 64-bit) 2 0.333 1 2 - - 2*u1-6
SUB (register, asr, 32-bit) 2 0.333 1 2 - - 2*u1-6
SUB (register, asr, 64-bit) 2 0.333 1 2 - - 2*u1-6
SUBS (extend) 2 0.667 1 2 - - 2*u1-3
SUBS (sxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (sxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (uxtb, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (uxtb, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (sxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (sxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (uxth, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (uxth, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (sxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (uxtw, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS 1 0.333 1 1 - - u1-3
SUBS (uxtw, 32-bit) 1 0.333 1 1 - - u1-3
SUBS (sxtw, 32-bit) 1 0.333 1 1 - - u1-3
SUBS (uxtx, 64-bit) 1 0.333 1 1 - - u1-3
SUBS (sxtx, 64-bit) 1 0.333 1 1 - - u1-3
SUBS (immediate, 32-bit) 1 0.333 1 1 - - u1-3
SUBS (immediate, 64-bit) 1 0.333 1 1 - - u1-3
SUBS (shifted immediate, 32-bit) 1 0.333 1 1 - - u1-3
SUBS (shifted immediate, 64-bit) 1 0.333 1 1 - - u1-3
SUBS (register, 32-bit) 1 0.333 1 1 - - u1-3
SUBS (register, 64-bit) 1 0.333 1 1 - - u1-3
SUBS (shift) 2 0.667 1 2 - - 2*u1-3
SUBS (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
SUBS (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
SWPA (32-bit) 3 2 - 2 - SWPA (64-bit) 3.047 2 - 2 - SWPB 3 2 - 2 - SWPAB 3 2 - 2 - SWPALB 7 2 - 2 - SWPLB 7 2 - 2 - SWPH 3 2 - 2 - SWPAH 3 2 - 2 - SWPALH 7 2 - 2 - SWPLH 7 2 - 2 - SXTW 1 0.167 1 1 - - u1-6 TBNZ (not taken) 0.5 1 1 - - u1/2 TBNZ (taken) 1 1 1 - - u1/2 TBZ (not taken) 0.5 1 1 - - u1/2 TBZ (taken) 1 1 1 - - u1/2 TST (shift) 2 0.667 1 2 - - 2*u1-3
TST (register, lsl, 32-bit) 2 0.667 1 2 - - 2*u1-3
TST (register, lsl, 64-bit) 2 0.667 1 2 - - 2*u1-3
TST (register, lsr, 32-bit) 2 0.667 1 2 - - 2*u1-3
TST (register, lsr, 64-bit) 2 0.667 1 2 - - 2*u1-3
TST (register, asr, 32-bit) 2 0.667 1 2 - - 2*u1-3
TST (register, asr, 64-bit) 2 0.667 1 2 - - 2*u1-3
UDIV (fast, 32-bit) 7 2 1 1 - - u5 UDIV (slow, 32-bit) 8 2 1 1 - - u5 UDIV (fast, 64-bit) 7 2 1 1 - - u5 UDIV (medium, 64-bit) 8 2 1 1 - - u5 UDIV (slow, 64-bit) 9 2 1 1 - - u5 UMADDL [1;3] 1 1 1 - - u6 UMNEGL 3 0.5 1 1 - - u5/6 UMSUBL [1;3] 1 1 1 - - u6 UMULH 3 0.5 1 1 - - u5/6 UMULL 3 0.5 1 1 - - u5/6 UXTB 1 0.167 1 1 - - u1-6 UXTH 1 0.167 1 1 - - u1-6 XAFLAG 1 0.333 1 1 - - u1-3 YIELD 0.129 1 - - - -