Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

DSB (NSHST)

Test 1: uops

Code:

  dsb nshst

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)696a6d6emap rewind (75)map stall (76)dispatch uop (78)map ldst uop (7d)8283flush restart other nonspec (84)85inst all (8c)inst barrier (9c)st unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)f5f6f7f8fd
100417032128000001701715801100010001000600049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032128000001701715801100010001000600049139521486717032316890100010001703217032111001100010000073116111690810001703317033170331703317033
100417032127000001701715801100010001000600049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032127000001701715801100010001000600049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032127100001701715801100010001000600049139521486317032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032128001600170171580110001000100060004913952148591703231689010001000170321703211100110001000136873116111683810001703317033170331703317033
1004170321270005101701715801100010001000600049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033
100417032127000001701715801100010001000600049139521486317032316890100010001703217032111001100010000073116111683810001703317033170331703317033
1004170321280000017017158011000100010006000491395214859170323168901000100017032170321110011000100000119116111683810001703317033170331703317033
100417032127000001701715801100010001000600049139521485917032316890100010001703217032111001100010000073116111683810001703317033170331703317033

Test 2: throughput

Code:

  dsb nshst

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4151schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
1020417003212740003017001701597001010010010000100100005005980004916695215093517003231687401010020010000200170032135919111020110099100100100001000100000014840071011611169838010000100170033170033170033170033170033
1020417003212740000017001701597001010010010000100100005005980004916695215100617003231687401010020010000200170032156521111020110099100100100001000100000000071011611169838010000100170033170033170033170033170033
1020417019012730000017001701597001010010010000100100005005980004916695215093717003231687401010020010000200170032135919111020110099100100100001000100000000071011611169838010000100170033170187170033170033170033
1020417003212740000017001701597001010010010000100100005005980004916695215098717003231687401010020010000200170032135919111020110099100100100001000100000000071011611169838010000100170033170033170033170033170033
1020417003212740000017001701597001010010010000100100005005980004916695215093517005631687401010020010000200170032135919111020110099100100100001000100002030071011611169838010000100170033170033170033170033170033
10204170032127300012017001701597001010010010000100100005005980004916695215101217003231687401010020010000200170032135919111020110099100100100001000100000000071011611169838010000100170033170033170033170033170033
10204170032127410014732817001701597001010010010000100100005005980004916695215093517003231687401010020010000200170032135919111020110099100100100001000100000000071011611169838010000100170033170033170033170033170033
1020417003212740000017001701597001010010010000100100005005980004916695215093517003231687401010020010000200170032135919111020110099100100100001000100001200071011611169838010000100170033170047170033170033170033
10204170032127300000170017015970010100100100001001000050059800049166952150991170032316874010100200100002001700321359191110201100991001001000010001000000150071011611169838010000100170033170033170033170033170191
1020417003212730000017001701597001010010610000100100005005980014916695215093517003231687401010020010000200170032135919111020110099100100100001000100000000071011611169838010000100170033170033170033170033170033

1000 unrolls and 10 iterations

Result (median cycles for code): 17.0032

retire uop (01)cycle (02)0318191e3f414b51schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)60696a6b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst barrier (9c)9fst unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? int retires (ef)f5f6f7f8fd
10024170032127400017001700159786100101010000101000050599801491669520149957170032316876210010201000020170032170032111002110910101000010100000000006406165616983801000010170033170033170033170033170033
10024170032127300017001700159786100101010000101000050599800491669520150026170032316876210010201000020170032170032111002110910101000010100000000016406166616983801000010170033170033170033170033170033
100241700321274001217001700159786100101010000101000050599800491669520149957170032316876210010201000020170032170032111002110910101000010100000920006405167616983801000010170033170033170033170033170033
1002417003212730001700170115978610010101000010100005059980149166952014995717003231687621001020100002017003217003211100211091010100001010000014100006406165516983801000010170033170033170033170033170038
10024170032127400017001700159786100101010000101000050599801491669520150141170032316876210010201000020170032170032111002110910101000010100000000006406166616983801000010170033170033170033170033170038
100241700321273000170017001597861001010100001010000505998014916695201499571700323168762100102010000201700321700321110021109101010000101000076300006406166616983801000010170033170033170033170033170038
1002417003213190001700170015978610010101004310100005059980049166985014995717003231687621001020100002017003217003211100211091010100001010000125600006405167516983801000010170033170033170033170033170038
10024170032127300017003300159786100541010000101000050599801491669520149957170032316876210010201000020170032170032111002110910101000010100000300006406165516983801000010170033170033170033170033170038
1002417003212740001700170015978610010101000010100005059980049166952014995717003231687621001020100002017003217003211100211091010100001010000107000006406166616983801000010170033170033170033170033170038
10024170032127300017001720159786100101010000101000050599801491669520149957170032316876210010201000020170032170032111002110910101000010100000000006406166516983801000010170033170033170033170033170038