Firestorm: CBNZ (taken) measurements

Code:

  cbnz x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	f5	f6	f7	f8	fd
1004	3120	18	2	2	0	0	50	25	1000	1000	1000	5000	0	2056	1942	3	18	1000	1000	1000	1962	1890	1	1	1001	1000	1000	0	0	1932	659	1036	464	417	1971	1847	1989	1983	2085	1965
1004	2074	15	1	1	0	0	62	25	1000	1000	1000	5000	1	1988	1976	3	18	1000	1000	1000	2060	1950	1	1	1001	1000	1000	0	0	1958	473	992	496	449	1967	1959	1977	1925	2069	2081
1004	1902	15	0	1	0	0	35	25	1000	1000	1000	5000	1	1986	1966	3	18	1000	1000	1000	2042	1996	1	1	1001	1000	1000	0	0	1948	517	940	478	418	1941	2015	1907	1995	1977	2015
1004	2146	15	0	0	0	0	33	25	1000	1000	1000	5000	1	1992	1972	3	18	1000	1000	1000	1966	1864	1	1	1001	1000	1000	0	12	1980	471	822	431	525	1861	2059	1987	1845	2017	1993
1004	2104	14	0	1	0	0	41	25	1000	1000	1000	5000	1	2038	1980	3	18	1000	1000	1000	1958	2100	1	1	1001	1000	1000	0	0	1976	476	960	507	465	2043	2055	1965	1959	2055	2019
1004	2090	15	0	0	0	0	35	25	1000	1000	1000	5000	0	1966	2000	3	18	1000	1000	1000	1976	2116	1	1	1001	1000	1000	0	0	2004	475	816	438	523	1929	2081	1979	1867	2009	2081
1004	1850	15	0	1	0	0	41	25	1000	1000	1000	5000	1	1998	2202	3	18	1000	1000	1000	1958	1926	1	1	1001	1000	1000	2	0	1914	486	954	525	512	1933	2009	1977	1873	2067	2015
1004	2056	14	0	1	0	0	35	25	1000	1000	1000	5000	1	2020	1974	3	18	1000	1000	1000	1960	1930	1	1	1001	1000	1000	0	0	1966	430	1004	501	484	2153	1965	2095	1999	1999	1949
1004	1914	14	0	0	0	0	35	25	1000	1000	1000	5000	1	1976	1882	3	18	1000	1000	1000	1968	1994	1	1	1001	1000	1000	6	3	2022	458	988	475	476	1913	1959	2071	1959	2043	1949
1004	2004	15	0	0	0	0	41	25	1000	1000	1000	5000	1	1874	2174	3	18	1000	1000	1000	1962	1964	1	1	1001	1000	1000	0	3	1884	504	916	443	458	1893	1959	1971	1901	2011	1993

Count: 8

Code:

  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0102

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int retires (ef)	f5	f6	f7	f8	fd
80204	81035	606	2	0	0	0	0	0	0	0	0	0	18	139	27	80105	80105	80107	400530	1	49	77736	80812	80818	6	10	80107	80207	80207	80916	64776	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	0	0	1	1	1	80801	457	1081	315	335	80809	100	80809	80811	80805	80809	80811
80204	80806	605	2	0	0	0	0	0	0	0	0	0	18	139	27	80105	80105	80107	400530	1	49	77730	80816	80812	6	10	80107	80207	80207	80902	64776	2	1	80201	80100	80099	100	100	100	0	0	0	0	0	0	0	1	1	1	80785	342	1041	312	338	80823	100	80815	80811	80807	80815	80811
80204	80814	755	2	0	0	0	0	0	0	0	0	0	18	145	27	80105	80105	80107	400530	1	49	77738	80822	80816	6	10	80107	80207	80207	80904	64778	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	0	0	1	1	1	80795	338	1053	311	338	80815	100	80811	80817	80817	80815	80813
80204	80812	624	2	0	0	0	0	0	0	0	0	0	18	139	27	80105	80105	80107	400530	1	49	77736	80820	80812	6	10	80107	80207	80207	80916	64778	5	1	80201	80100	80099	100	100	100	0	0	0	0	0	0	0	1	1	1	80797	341	1107	313	338	80815	100	80819	80815	80821	80817	80813
80204	80814	605	2	0	0	0	0	0	0	0	0	0	18	424	27	80105	80105	80107	400530	1	49	77734	80824	80814	6	10	80107	80207	80207	80908	64780	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	0	0	1	1	1	80795	330	1047	312	342	80815	100	80815	80809	80807	80817	80817
80204	80808	605	2	0	0	0	0	0	0	0	0	0	18	145	27	80105	80105	80107	400530	1	49	77726	80816	80814	6	10	80107	80207	80207	80908	64788	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	0	0	1	1	1	80799	336	1073	311	337	80815	100	80823	80823	80817	80811	80823
80204	80812	605	2	0	0	0	0	0	0	0	0	0	18	139	27	80105	80105	80107	400530	1	49	77730	80808	80808	6	10	80107	80207	80207	80904	64780	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	48	0	1	1	1	80793	339	1111	312	336	80811	100	80815	80811	80807	80807	80809
80204	80806	605	2	0	0	0	0	0	0	0	0	0	19	145	27	80105	80105	80107	400530	1	49	77738	80816	80814	6	10	80107	80207	80207	80926	64776	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	0	0	1	1	1	80809	344	1071	317	346	80823	100	80817	80809	80817	80817	80809
80204	80810	605	2	0	0	0	0	0	0	0	0	0	18	145	27	80105	80105	80107	400530	1	49	77734	80812	80814	6	10	80107	80207	80207	80920	64788	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	0	0	1	1	1	80795	338	1095	314	338	80807	100	80815	80817	80817	80815	80811
80204	80808	605	2	0	0	0	0	0	0	0	3	0	18	147	27	80105	80105	80107	400530	1	49	77740	80812	80810	6	10	80107	80207	80207	80904	64784	1	1	80201	80100	80099	100	100	100	0	0	0	0	0	0	0	1	1	1	80787	336	1051	312	342	80813	100	80813	80829	80811	80813	80823

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	60	69	6a	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	ea	eb	? int retires (ef)	f5	f6	f7	f8	fd
80024	240113	1798	1	0	0	1	0	0	0	0	0	1	34	28	80011	80011	80012	400058	1	49	236968	0	240044	240046	6	10	80012	80022	80022	240044	240048	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	0	0	1	1	1	240021	0	79823	160014	0	79951	80001	240039	0	0	10	240045	240054	240045	240045	240045
80024	240040	1798	1	0	0	1	0	0	0	0	0	1	34	28	80011	80011	80012	400058	1	49	236958	0	240044	240042	6	10	80012	80022	80022	240042	240042	1	1	80021	80010	80009	10	10	10	0	0	0	1	0	838	0	1	1	1	240019	0	80001	160014	0	79991	80002	240044	0	0	10	240045	240045	240045	240041	240045
80024	240040	1798	1	0	1	1	0	3	3	12	0	1	217	28	80011	80011	80012	400058	0	49	236962	0	240301	240042	6	10	80060	80022	80028	240044	240040	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	3	0	1	1	1	240021	0	80001	160014	0	79992	80002	240041	0	0	10	240043	240043	240043	240300	240045
80024	240044	1798	1	0	1	1	0	0	0	12	0	1	34	28	80011	80011	80036	400058	0	49	236962	0	240042	240042	6	61	80012	80022	80046	240034	240042	1	1	80021	80010	80009	10	10	10	2	0	0	0	0	0	0	1	1	1	240021	0	80001	160017	0	79992	80002	240039	0	0	10	240041	240043	240043	240043	240043
80024	240040	1798	1	0	0	1	0	0	0	0	0	1	34	28	80011	80011	80012	400058	0	49	236962	0	240044	240042	6	10	80012	80022	80022	240042	240042	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	0	0	1	1	1	240021	0	80001	160014	0	79993	80001	240041	0	0	10	240045	240043	240041	240045	240045
80024	240044	1800	1	0	0	1	0	0	0	0	0	1	143	28	80035	80011	80012	400058	1	49	236964	0	240301	240044	18	10	80012	80046	80022	240044	240042	5	1	80021	80010	80009	10	10	10	0	0	0	0	0	0	0	1	1	1	240056	0	80002	160016	0	79992	80003	240183	0	0	10	240713	240399	240298	240045	240045
80024	240044	1798	0	0	0	1	0	0	8	12	88	1	76	28	80011	80011	80012	400058	1	49	236964	0	240040	240044	6	10	80012	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	2	0	6	0	1	1	1	240027	0	80000	160140	0	79993	80002	240261	0	0	10	240045	240045	240039	240045	240171
80024	240044	1798	3	0	0	1	0	0	0	0	0	1	76	28	80011	80011	80030	400058	1	49	236964	0	240044	240042	6	10	80012	80028	80022	240044	240040	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	3	0	1	1	1	240021	0	80002	160016	0	79992	80003	240041	0	0	10	240045	240043	240043	240043	240045
80024	240040	1798	3	1	0	1	0	0	0	0	0	1	604	28	80017	80011	80012	400058	1	49	236962	0	240044	240042	35	10	80012	80028	80022	240042	240042	1	1	80021	80010	80009	10	10	10	0	0	3	0	0	0	0	1	1	1	240021	0	80002	160016	0	79993	80003	240037	0	0	10	240045	240094	240045	240043	240045
80024	240044	1798	1	0	0	1	0	0	0	0	0	1	699	28	80011	80011	80012	400058	1	49	236962	0	240044	240042	6	10	80103	80022	80022	240044	240044	1	1	80021	80010	80009	10	10	10	0	0	0	0	0	0	2	1	1	1	240021	0	80001	160016	0	79993	80003	240041	0	0	10	240045	240045	240045	240045	240043

CBNZ (taken)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations