Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

TST (register, lsr, 32-bit)

Test 1: uops

Code:

  tst w0, w1, lsr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
100470950611000304252000200010004087717097094982535611000100020007097811100110000073222226842000710710710710710
100470950611000304252000200010004087717097094982135611000100020007097811100110000073222226842000710710710710710
100470950611000304252000200010004087717097094982135611000100020007097811100110000073222226842000710710710710710
100470950821000304252000200010004087717097094982535611000100020007097811100110000073222226842000710710710710710
100470956611000304252000200010004087717097094982135611000100020007097811100110000073222226842000710710710710710
100470960611000304252000200010004087717097094982135611000100020007097811100110000073222226842000710710710710710
100470960611000304252000200010004087717097094982535611000100020007097811100110000073222226842000710710710710710
100470960611000304252000200010004087717097094982135611000100020007097811100110000073222226842000710710710710710
100470950611000304252000200010004087717097094982135611000100020007097811100110000073222226842000710710710710710
1004709501221000304252000200010004087717097094982535611000100020007097811100110000073222226842000710710710710710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  tst w0, w1, lsr #17
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
2020430035225000025410000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522400006110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522501006110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
2020430035225005706110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363008230036
202043003522500006110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352250611000029891253001030010200101956289049269550300353003527391327498200102002030020300351451120021109102001010010010001270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100100340601270233212995830000100103003630036300363003630036
200243003522507261000029891253001030010200101956289049269550300353003527391327498200102002030020300351451120021109102001010010000301270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100100380408301270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100100100001270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100100280301270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100100290601270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562891492695503003530035273913274982001020020300203003514511200211091020010100100300601270133112995830000100103003630036300363003630036
20024300352250611000029891253001030010200101956289049269550300353003527391327498200102012830020300351451120021109102001010010030301270133112995830000100103003630036300363003630036
200243003522506110000298912530010300102001019562890492695503003530035273913274982001020020300203003514511200211091020010100100360301270133112995830000100103003630036300363003630036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  tst w0, w1, lsr #17
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)0318191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
202043003522500006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101331222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101331222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561981492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110000298932530100301002010019561980492695530035300352736932747820100202003020030035145112020110099100201001010000013101231222995430000101003003630036300363003630036
202043003522500006110005298932530100301002010019561980492695530035300352736932747820100202003020030070145112020110099100201001010000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522401026100002989125300103001020010195628914926955030035300352739132749820010200203002030035145112002110910200101001001270133112995830000100103003630036300363003630036
20024300352250375100002989125300103001020010195628914926955030035300352739132749820010200203002030035145112002110910200101001001270133112995830000100103003630036300363003630036
200243003522501051100002989125300103001020010195628914926955030035300352739132749820010200203002030035145112002110910200101001001270133112995830000100103003630036300363003630036
20024300352250913100002989125300103001020010195628914926955030035300352739132749820010200203002030035145112002110910200101001001270133112995830000100103003630036300363003630036
200243003522501132100002989125300103001020010195628914926955030035300352739132749820010200203002030035145112002110910200101001011270133112995830000100103003630036300363003630036
20024300352250935100002989125300103001020010195628914926955030035300352739132749820010200203002030035145112002110910200101001001270133112995830000100103003630036300363003630036
20024300352250853100002989125300103001020010195628914926955030035300352739132749820010200203002030035145112002110910200101001001270133112995830000100103003630036300363003630036
2002430035225061100002989125300103001020010195628914926955030035300352739132749820010200203002030035145112002110910200101001001270133112995830000100103003630036300363003630036
20024300352250944100002989125300103001020010195628914926955030035300352739132749820010200203002030035145112002110910200101001001270133212995830000100103003630036300363003630036
200243003522501012100002989125300103001020010195628914926955030035300352739132749820010200203002030035145112002110910200101001001270133212995830000100103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  tst w0, w1, lsr #17
  tst w0, w1, lsr #17
  tst w0, w1, lsr #17
  tst w0, w1, lsr #17
  tst w0, w1, lsr #17
  tst w0, w1, lsr #17
  tst w0, w1, lsr #17
  tst w0, w1, lsr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045345640100001680618000048741251601001601008010034400054950330534105341043298206334336080100802001602005341078118020110099100801001000000000511022411533921600001005341153411534115341153411
8020453410400000000618000048741251601001601008010034400054950330534105341043298205034336080100802001602005341078118020110099100801001000000000511012411533921600001005341153411534115341153411
80204534104000000330618000048741251601001601008010034400054950330534105341043298206334336080100802001602005341078118020110099100801001000000000511012411533921600001005341153411534115341153411
80204534104000000660618000048741251601001601008010034400054950330534105341043298205034336080100802001602005341078118020110099100801001000000000511012411533921600001005341153411534115341153411
802045341040000001501918000048741251601001601008010034400054950330534105341043298206334336080100802001602005341078118020110099100801001000000000511012411533921600001005341153411534115341153411
80204534104000000270618000048741251601001601008010034400054950330534105341043298205034336080100802001602005341078118020110099100801001000000000511012411533921600001005341153411534115341153411
80204534104000000300618000048741251601001601008010034400054950330534105341043298206334336080100802001602005341078118020110099100801001000000000511012411533921600001005341153411534115341153411
8020453410400000000848000048741251601001601008010034400054950330534105341043298205034336080100802001602005341078118020110099100801001000000000511022421533921600001005341153411534115341153411
8020453410399000042061800004874125160100160100801003440005495033053410534104329820633433608010080200160200534107811802011009910080100100000007560511012411533921600001005341153411534115341153411
80204534104000000420618000048741251601001601008010034400054950330534105341043298206034336080100802001602005341078118020110099100801001000000000511011711533921600001005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)5f60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaeb? int retires (ef)f5f6f7f8fd
800245340240002046800004794625160010160010800103438130014950300533805338043290270734335280010800201600205338078118002110910800101005020000142400016165335916000000105338153381533815338153381
80024533804000197880000479462516001016001080010343813001495030053380533804329027073433528001080020160020533807811800211091080010100502000016240001665335916000000105338153381533815338153381
800245338039906180000479462516001016001080010343813001495030053380533804329025623433528001080020160020533807811800211091080010100502000016240006165335916000000105338153381533815338153381
80024533804000183580000479462516001016001080010343813001495030053380533804329025623433528001080020160020533807811800211091080010100502000016240001665335916000000105338153381533815338153381
8002453380400019988000047946251600101600108001034381300198503005338053380432902707343352800108002016002053380781180021109108001010050200001624000161653359160000200105338153381533815338153381
80024533804000188180000479462516001016001080184343813001495030053380533804329027073433528001080020160020533807811800211091080010100502000016170006135335916000000105338153381533815338153381
8002453380399020818000047946251600101600108001034381300149503005338053380432902707343352800108002016002053380781180021109108001010050200006240001665335916000000105338153381533815338153381
800245338039909938000047946251600101600108001034381300149503005338053380432902562343352800108002016002053380781180021109108001010050200006240001665335916000000105338153381533815338153381
80024533804000250680000479462516001016001080010343813001495030053380533804329027073433528001080020160020533807811800211091080010100502000016240006165335916000000105338153381533815338153381
80024533804000618000047946251600101600108001034381300149503005338053380432902707343352800108002016002053380781180021109108001010050200006240001665335916000000105338153381533815338153381