Firestorm: STLXRB measurements

Code:

  stlxrb w0, w1, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 50.674

Integer unit issues: 0.000

Load/store unit issues: 50.674

SIMD/FP unit issues: 0.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	22	3f	4f	51	schedule uop (52)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	60	64	69	6a	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int store (96)	inst ldst (9b)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	f5	f6	f7	f8	fd
1005	37993	285	0	0	0	2	0	2013	0	0	37978	0	7267	50674	50674	87814	1003189	1	1000	49	34913	37993	37993	13140	5945	24394	87814	91436	182920	37995	37993	1001	1	1001	1000	1000	44965	0	44965	0	44965	2	0	1998	44965	1000	0	1000	0	0	16595	37	2063	25	19	37909	1000	37994	37994	37994	37994	37994
1004	37993	284	0	0	0	0	0	1998	0	1	37978	0	7267	50674	50674	87814	1003204	0	1000	49	34913	37993	37993	13140	5937	24398	87814	91437	182986	37993	37993	1001	1	1001	1000	1000	44965	0	44965	0	44965	0	0	1998	44965	1000	0	1000	0	0	16595	22	2059	24	19	37909	1000	37994	37994	37994	37994	37994
1004	37993	284	0	0	0	0	0	1998	0	0	37986	5	7274	50687	50676	87816	1003590	0	1000	49	34921	38001	38001	13147	5940	24402	87816	91437	182874	37993	37994	1001	1	1001	1000	1000	45002	0	44967	0	44965	0	0	1998	44965	1000	0	1000	0	0	16595	22	2063	29	28	37909	1000	37994	37994	37994	37994	37994
1004	37996	285	0	0	0	0	0	1998	0	0	37986	0	7267	50672	50673	87816	1003593	0	1000	49	34921	38001	38001	13147	5937	24404	87816	91436	182872	38004	37994	1001	1	1001	1000	1000	44965	0	44965	0	44965	0	0	1998	44965	1000	0	1000	0	0	16595	23	2063	22	27	37917	1000	38002	38002	38002	38002	38002
1004	38001	285	1	0	0	3	1	1998	14	0	37978	0	7267	50674	50674	87814	1003204	0	1000	49	34913	37993	37993	13140	5937	24395	87814	91437	182874	38009	37994	1001	1	1001	1000	1000	44965	0	44965	0	44965	0	0	1998	44965	1000	0	1000	0	0	16595	27	2063	24	26	37917	1000	38002	38002	38002	38002	38002
1004	38001	285	1	0	1	0	0	1998	15	0	37978	0	7267	50674	50674	87814	1003204	0	1000	49	34913	37993	37993	13140	5945	24394	87814	91437	182874	37994	37993	1001	1	1001	1000	1000	44965	0	44965	0	44965	0	0	1998	44965	1000	0	1000	0	0	16595	24	2053	19	28	37909	1000	37994	37994	37994	37994	37994
1004	37993	284	0	0	0	0	0	1998	0	0	37978	0	7267	50674	50674	87814	1003204	0	1000	49	34913	37993	37993	13140	5943	24394	87814	91437	182938	37995	37994	1001	1	1001	1000	1000	44965	0	44965	0	44967	0	0	2005	44965	1000	0	1000	0	0	16595	26	2063	29	24	37909	1000	37994	37994	37994	37994	37994
1004	37993	284	0	0	0	0	0	1998	0	0	37978	0	7267	50674	50674	87814	1003204	0	1000	49	34913	37993	37993	13140	5937	24400	87814	91437	182874	37997	38002	1001	1	1001	1000	1000	44965	0	44965	0	44965	0	0	1998	44965	1000	0	1000	0	0	16595	24	2063	23	27	37917	1000	38002	38002	38002	38002	38002
1004	38001	285	1	1	0	0	0	1998	15	1	37978	0	7267	50674	50674	87814	1003204	0	1000	49	34913	37993	37993	13140	5949	24394	87814	91437	182874	37994	37993	1001	1	1001	1000	1000	44965	0	44965	0	44965	0	0	1998	44965	1000	0	1000	0	0	16595	23	2061	23	24	37917	1000	38002	38002	38002	38002	38002
1004	38001	284	1	0	0	0	0	1998	14	0	37978	0	7267	50674	50674	87814	1003204	0	1000	49	34913	37993	37993	13140	5937	24402	87814	91437	182890	37993	37993	1001	1	1001	1000	1000	44965	0	44965	0	44965	0	0	1998	44965	1000	0	1000	0	0	16595	22	2063	25	23	37909	1000	37994	37994	37994	37994	37994

Test 2: throughput

Code:

  stlxrb w0, w1, [x6]
  add x6, x6, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.9156

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	24	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	l1d cache miss st nonspec (c0)	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20206	389355	2916	1	0	1	1	0	0	20066	0	70	0	0	0	0	81	0	389113	8	0	69404	558500	298924	259576	788865	697489	12744667	11717702	0	10000	0	49	386170	0	389189	389271	83466	59210	181296	1486282	794497	778604	794512	1557210	389128	389252	10001	1	20201	100	99	100	10000	10100	10000	100	229648	0	32855	0	0	0	229648	1	0	0	0	19998	229648	10000	1568	0	0	209452	1	55	10978	53	35	389190	291423	10000	10100	389128	389253	389251	389128	389251
20204	389250	2916	0	0	0	0	0	0	20010	0	142	1	0	0	0	117	0	389112	59	0	69402	558500	298924	259576	788796	697528	12745418	11716917	0	10000	14	49	386172	0	389127	389250	83464	59206	181296	1486284	794657	778663	794497	1557556	389128	389252	10001	1	20201	100	99	100	10000	10100	10000	100	229798	0	44624	9	0	152	229648	1	0	152	146	20001	229794	10000	1985	0	0	209452	1	55	10970	53	59	389189	291423	10000	10100	389127	389128	389253	389250	389128
20204	389250	2916	0	0	0	0	0	0	20004	0	140	1	0	0	0	83	0	389113	23	64	69279	558500	298924	259576	788797	697486	12744786	11716921	0	10000	0	49	386048	0	389250	389127	83466	59202	181178	1486286	794474	778665	794499	1557326	389250	389250	10001	1	20201	100	99	100	10000	10100	10000	100	229731	0	25130	1	0	84	229680	6	2	75	66	20010	229705	10000	1424	0	0	209452	1	55	10978	53	59	389067	291423	10000	10100	389129	389380	389897	389252	389128
20204	389250	2915	0	0	0	0	0	0	19998	0	28	0	0	0	0	54	0	389177	31	0	69279	558500	298924	259576	788799	697486	12744650	11716921	0	10000	0	49	386173	0	389252	389252	83529	59088	181180	1486283	794497	778665	794517	1557208	389126	389250	10001	1	20201	100	99	100	10000	10100	10000	100	229776	0	33959	9	0	125	229648	1	0	125	118	20001	229773	10000	1616	0	0	209452	1	55	10976	53	59	389192	291423	10000	10100	389128	389127	389253	389129	389129
20204	389128	2915	0	0	0	0	0	0	20004	0	150	1	0	0	0	70	0	389113	14	0	69404	558500	298924	259576	788798	697526	12744703	11716921	1	10000	0	49	386172	0	389127	389250	83527	59080	181298	1486259	794472	778664	794485	1557326	389250	389127	10001	1	20201	100	99	100	10000	10100	10000	100	229783	0	39103	8	0	136	229648	1	0	126	120	19998	229776	10000	1744	0	0	209452	1	55	10978	53	59	389067	291423	10000	10100	389251	389253	389250	389128	389129
20204	389128	2914	0	0	0	0	0	0	19998	0	140	1	0	0	0	114	0	389113	45	0	69429	558520	298924	259576	788773	697486	12744605	11717665	0	10000	0	49	386169	0	389127	389127	83466	59202	181170	1486259	794474	778735	794499	1557208	389250	389127	10001	1	20201	100	99	100	10000	10100	10000	100	229790	0	39839	9	0	142	229648	2	0	142	136	20001	229790	10000	1712	0	0	209535	1	55	10978	53	59	389192	291423	10000	10100	389253	389128	389253	389128	389128
20204	389126	2914	0	0	0	0	0	0	20004	0	138	1	0	0	0	114	0	389274	47	0	69279	558500	298924	259576	788796	697486	12744578	11717702	0	10000	0	49	386182	0	389127	389128	83468	59210	181173	1486259	794499	778665	794470	1557200	389127	389127	10001	1	20201	100	99	100	10000	10100	10000	100	229752	0	30644	11	0	108	229665	3	0	108	98	20001	229736	10000	1600	0	0	209452	1	55	10978	53	59	389192	291425	10000	10100	389128	389250	389128	389253	389128
20204	389127	2914	0	0	0	0	0	0	20004	0	91	2	0	0	0	50	0	389237	0	0	69404	558500	298924	259576	788796	697486	12744650	11716933	0	10000	0	98	386172	0	389127	389250	83530	59218	181301	1486286	794471	778606	794514	1557334	389249	389252	10001	1	20201	100	99	100	10000	10100	10000	100	229648	0	32118	0	0	0	229648	0	0	0	0	19998	229648	10000	1872	0	0	209452	1	55	10978	53	59	389192	291423	10000	10100	389129	389253	389253	389129	389129
20204	389250	2915	0	0	0	0	0	0	19998	0	48	2	0	0	0	51	0	389235	4	0	69402	558500	298924	259576	788774	697486	12744644	11717615	0	10000	0	49	386047	0	389127	389250	83529	59125	181298	1486260	794496	778665	794498	1557200	389127	389126	10001	1	20201	100	99	100	10000	10100	10000	100	229648	0	36530	0	0	0	229648	1	2	41	70	20004	229670	10000	1184	1	0	209452	1	55	10978	53	59	389192	291425	10000	10100	389251	389128	389251	389253	389128
20204	389249	2915	0	0	0	0	0	4	20606	352	98	0	0	0	0	50	0	389112	0	0	69279	558500	298924	259576	788796	697486	12744630	11716921	0	10000	0	49	386047	0	389128	389249	83529	59204	181295	1486257	794472	778605	794517	1557330	389127	389127	10001	1	20201	100	99	100	10000	10100	10000	100	229688	0	40213	0	0	99	229648	1	0	103	90	19998	229756	10000	1248	0	0	209452	1	54	10978	53	59	389192	291423	10000	10100	389253	389128	389250	389251	389128

1000 unrolls and 10 iterations

Result (median cycles for code): 38.9948

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	20	22	23	29	3a	3e	3f	40	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	l1d cache miss ld (a3)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	aa	ab	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20026	389970	2921	1	0	2	0	8	1	4	0	19998	7	14	2	0	0	56	64	389943	39	4	70099	550218	290552	259664	760282	697574	12689805	11765061	0	10000	0	49	387134	0	389956	389957	70817	59890	188870	1457820	760818	759425	760823	1518338	390169	44	10001	1	20021	10	9	10	10000	10010	10000	10	229855	10	32138	8	0	111	229766	1	1	106	130	20118	229872	10000	7	960	1	2	2	200996	50	10974	51	53	390105	289801	10000	10010	390218	389945	389958	389957	389957
20024	389956	2923	1	6	1	0	0	1	0	0	20015	359	95	1	0	0	0	0	389929	35	3	70100	550216	290552	259716	760292	697574	12689770	11767448	0	10000	0	49	386864	0	390188	389944	70817	59892	188873	1457827	760820	759170	760822	1518338	389955	44	10001	1	20021	10	9	10	10000	10010	10000	10	229743	9	32872	0	0	0	229743	4	1	0	0	22148	229736	10000	7	1408	1	1	0	200998	56	10976	46	53	389896	289826	10000	10010	389945	389947	390174	389956	389956
20024	389957	2920	1	0	1	0	0	1	3	0	19998	95	0	0	0	0	44	0	389929	28	4	70100	550369	290552	259664	760248	697574	12689796	11768023	0	10000	0	49	386876	0	389944	389955	70822	59900	188863	1458219	760818	759169	760822	1518338	389955	44	10001	1	20021	10	9	10	10000	10010	10000	10	229815	24	27722	0	0	0	229743	0	1	0	0	20005	229736	10000	7	1376	1	2	0	200998	53	10978	51	53	389884	289801	10000	10010	389956	389956	389945	389956	389945
20024	390218	2921	1	1	1	1	0	1	0	0	19998	7	81	2	0	0	20	0	389929	30	2	70099	550216	290552	259664	760252	697574	12689762	11765149	0	10000	14	49	386864	0	390249	389955	70872	59924	188864	1457826	760818	759169	761004	1518348	389956	44	10001	1	20021	10	9	10	10000	10010	10000	10	229744	7	34346	0	0	7	229743	0	1	0	0	20026	229736	10000	7	2080	1	1	0	200995	53	10978	43	53	389884	289801	10000	10010	389982	389946	389956	389956	389957
20024	389944	2920	1	0	0	0	0	1	4	0	20004	7	91	2	0	0	36	0	389929	26	3	70100	550216	290566	259664	760248	697574	12689908	11765035	0	10000	0	49	386876	0	389955	389955	70816	59888	188856	1457821	761031	759180	760822	1518342	389946	44	10001	1	20021	10	9	10	10000	10010	10000	10	229866	7	38024	11	0	121	229743	3	1	123	106	20011	229834	10000	7	1152	1	1	0	200998	53	10970	45	54	389895	289806	10000	10010	389945	389945	389956	389945	389945
20024	389945	2921	1	0	1	1	0	1	0	0	19998	7	79	0	0	0	40	0	389940	20	2	70088	550216	290552	259664	760247	697574	12689768	11765172	1	10000	0	49	386875	0	389944	389944	70822	59901	188853	1457828	760819	759169	760818	1518348	389944	44	10001	1	20021	10	9	10	10000	10010	10000	10	229835	8	32879	10	0	98	229743	0	1	88	74	20008	229836	10000	7	1536	1	1	0	200998	53	10978	50	56	389884	289801	10000	10010	389956	389956	389946	389945	389956
20024	389944	2921	1	0	1	0	0	1	0	0	19998	7	0	0	0	0	12	0	389929	0	3	70287	550216	290552	259664	760252	697574	12689762	11765087	0	10000	0	49	386876	0	389956	390272	70822	59900	188856	1457826	760817	759272	760819	1518342	389956	44	10001	1	20021	10	9	10	10000	10010	10000	10	229771	9	25514	3	0	7	229743	0	0	65	60	20011	229835	10000	7	1312	1	2	2	200998	53	10978	51	48	389895	289801	10000	10010	389945	389956	389945	389956	389945
20024	389944	2921	1	0	1	0	1	1	0	0	20004	7	72	1	0	0	41	0	389931	12	2	70088	550216	290552	259664	760252	697574	12689777	11765175	0	10000	0	49	386864	0	389944	389956	70817	59888	188853	1457826	760825	759168	760822	1518338	389945	44	10001	1	20021	10	9	10	10000	10010	10000	10	229753	8	28458	0	0	2	229743	0	2	0	0	20005	229831	10000	7	1152	1	1	0	200998	48	10978	52	47	389895	289801	10000	10010	389958	390201	389946	389945	389945
20024	389956	2921	1	0	0	0	0	0	0	0	19998	7	28	0	0	0	9	36	389940	8	2	70088	550216	290566	259664	760246	697574	12689762	11765135	0	10000	0	49	386875	0	389955	389955	70822	59900	188868	1457826	760818	759168	760822	1518334	389956	44	10001	1	20021	10	9	10	10000	10010	10000	10	229783	8	26986	6	0	37	229753	1	1	28	0	20005	229784	10000	7	1056	1	1	0	200999	54	10970	51	45	389896	289801	10000	10010	389945	389945	389945	389957	389957
20024	389956	2920	1	0	0	0	0	1	0	0	19998	7	108	1	0	0	48	0	389929	44	2	70088	550216	290552	259669	760247	697574	12689806	11765148	0	10000	0	49	386866	0	389957	389956	70815	59900	188856	1457828	760817	759171	760822	1518344	389955	44	10001	1	20021	10	9	10	10000	10010	10000	10	229776	7	30666	3	0	120	229743	0	0	117	102	20008	229852	10000	8	1088	1	0	0	200998	53	10974	51	53	389886	289801	10000	10010	389984	389957	389956	389957	389945

Test 3: throughput

Code:

  stlxrb w0, w1, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 38.0107

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	l1d cache miss st nonspec (c0)	c9	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10205	380118	2848	0	0	0	0	0	0	19998	0	1	0	0	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377027	0	380107	380107	130437	59951	248984	926439	19100	938443	19100	1876886	380109	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458866	10000	10000	0	10	172638	0	134	11072	131	131	380040	1198	10000	100	380108	380108	380108	380108	380109
10204	380107	2847	0	0	0	0	0	0	19998	0	1	0	181	380092	0	70271	529272	10697	518575	10697	915736	54384	10462001	1	10000	49	373996	0	380107	380107	130437	59955	248987	926435	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458866	10000	10000	0	10	172638	1	132	11064	132	132	380040	1197	10000	100	380110	380108	380108	380109	380123
10204	380109	2847	0	0	0	0	0	0	19998	0	1	0	180	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	373975	0	380110	380107	130437	59950	248979	926433	19100	938443	19100	1877438	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458870	0	458866	0	0	19998	458866	10000	10000	0	10	172636	1	131	11064	132	132	380042	1197	10000	100	380108	380108	380108	380108	380108
10204	380107	2847	0	0	0	0	0	0	19998	0	1	0	180	380092	0	70271	529272	10697	518575	10697	915736	54384	10461868	0	10000	49	377027	0	380107	380107	130437	59947	248979	926589	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458866	10000	10000	0	10	172636	1	131	11069	132	132	380040	1197	10000	100	380108	380108	380145	380108	380108
10204	380107	2847	0	0	0	0	0	0	20008	0	1	0	181	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377027	0	380107	380108	130437	59947	248979	926433	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	458906	0	0	19998	458866	10000	10000	0	10	172636	1	132	11072	132	132	380040	1197	10000	100	380137	380110	380145	380139	380171
10204	380109	2847	0	0	0	0	0	0	20789	0	0	1	180	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	0	10000	49	377027	0	380108	380107	130437	59951	248982	926433	19100	938443	19100	1876886	380107	380127	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458866	10000	10000	0	10	172636	1	132	11062	131	131	380043	1197	10000	100	380108	380108	380108	380108	380108
10204	380108	2847	0	0	0	0	0	0	19998	0	0	1	181	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377027	0	380107	380109	130437	59963	248989	926433	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458866	10000	10000	0	10	172636	1	132	11061	132	132	380041	1197	10000	100	380108	380111	380108	380108	380108
10204	380107	2847	1	0	0	0	0	0	19998	0	0	1	181	380094	0	70271	529272	10697	518575	10697	915808	54384	10461863	1	10000	49	377027	0	380107	380107	130437	59960	248992	926433	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458866	10000	10000	0	10	172636	1	132	11071	132	132	380041	1197	10000	100	380110	380108	380108	380108	380160
10204	380107	2847	0	0	0	0	0	0	20025	0	0	1	180	380092	0	70269	529281	10697	518575	10697	915736	54384	10461868	1	10000	49	377027	0	380107	380107	130437	59947	248979	926433	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458872	0	458866	0	458866	0	0	19998	458866	10000	10000	0	10	172638	1	132	11072	132	132	380064	1197	10000	100	380122	380126	380108	380108	380110
10204	380109	2847	0	0	0	0	0	0	19998	0	0	0	181	380092	0	70271	529272	10697	518575	10697	915736	54384	10461863	1	10000	49	377027	0	380107	380108	130437	59948	248979	926433	19100	938443	19100	1876886	380107	380107	10001	1	10201	100	99	100	10000	100	10000	100	458866	0	458866	0	458866	0	0	19998	458866	10000	10000	0	10	172638	1	132	11070	132	132	380071	1197	10000	100	380108	380111	380108	380108	380108

1000 unrolls and 10 iterations

Result (median cycles for code): 38.0019

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1d tlb fill (05)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	22	23	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	60	64	67	69	6a	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int store (96)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache miss st (a2)	a4	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	af	atomic or exclusive fail (b4)	bc	l1d cache miss st nonspec (c0)	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
10025	380019	2847	1	0	1	0	0	0	19998	14	1	0	0	380004	4	70267	519766	1067	518664	1067	915821	5424	10470771	0	10000	0	49	376939	0	380022	380019	138378	59939	249335	916873	1910	953891	1910	1907782	380054	380033	10001	1	10021	10	9	10	10000	10	10000	10	458973	14	458958	0	0	458972	0	0	20013	458957	10000	14	10000	1	1	169648	42	11081	41	41	379952	117	10000	10	380020	380020	380020	380020	380020
10024	380019	2846	1	0	1	1	0	0	19998	14	1	0	0	380004	0	70267	519731	1067	518667	1067	915806	5424	10470765	0	10000	0	49	376939	0	380019	380019	138355	59940	249343	916874	1910	953891	1910	1907782	380021	380019	10001	1	10021	10	9	10	10000	10	10000	10	458973	15	458957	0	0	458972	64	1	20033	458960	10000	14	10000	1	0	169648	42	11079	41	41	379953	117	10000	10	380021	380022	380020	380020	380021
10024	380019	2847	1	1	1	1	0	0	19998	14	1	0	0	380004	0	70267	519731	1067	518664	1067	915879	5424	10470768	0	10000	0	49	376939	0	380019	380019	138355	59949	249335	916874	1910	954274	1910	1909136	380478	380019	10001	1	10021	10	9	10	10000	10	10000	10	458973	15	458960	0	2	458971	0	1	20012	458958	10000	14	10000	1	2	169647	44	11070	41	41	379952	117	10000	10	380020	380020	380020	380020	380020
10024	380019	2846	1	1	0	0	0	0	20022	14	1	0	0	380004	0	70267	519731	1067	518665	1067	915806	5424	10470771	1	10000	0	49	376939	0	380019	380019	138355	59955	249335	916948	1910	953891	1910	1907894	380019	380019	10001	1	10021	10	9	10	10000	10	10000	10	458971	14	458958	0	0	458972	0	0	20012	458958	10000	14	10000	1	0	169648	42	11080	41	41	379952	117	10000	10	380021	380020	380020	380020	380020
10024	380019	2846	1	0	0	0	0	0	19998	14	0	0	0	380004	0	70268	519731	1067	518662	1067	915806	5424	10470768	0	10000	0	49	376939	0	380019	380019	138355	59955	249335	916874	1910	953891	1910	1907884	380019	380019	10001	1	10021	10	9	10	10000	10	10000	10	458972	16	458957	0	0	458972	0	2	20022	458958	10000	14	10000	1	2	169648	42	11074	44	44	379952	117	10000	10	380020	380020	380020	380020	380022
10024	380019	2847	1	1	1	1	0	0	20103	14	1	0	0	380004	4	70267	519730	1067	518664	1067	915807	5424	10470768	0	10000	0	98	376939	0	380019	380020	138358	59939	249337	916874	1910	953891	1910	1907814	380019	380019	10001	1	10021	10	9	10	10000	10	10000	10	458972	15	458956	0	1	458971	0	1	20012	458958	10000	14	10000	1	1	169648	42	11069	42	43	379952	117	10000	10	380021	380020	380020	380020	380020
10024	380019	2847	1	1	1	1	0	0	19998	14	0	0	0	380004	0	70267	519731	1067	518667	1067	915807	5424	10470765	0	10000	0	49	376940	0	380021	380019	138355	59939	249335	916874	1910	953891	1910	1907878	380019	380020	10001	1	10021	10	9	10	10000	10	10000	10	458972	14	458957	0	0	458956	0	0	19998	458956	10000	0	10000	0	0	169650	41	11080	41	41	379945	117	10000	10	380012	380012	380012	380012	380012
10024	380013	2847	0	0	0	0	0	0	19998	0	1	0	0	380004	4	70267	519730	1067	518666	1067	915807	5424	10472260	0	10000	0	49	376939	0	380019	380019	138355	59939	249345	916874	1910	953891	1910	1907788	380019	380019	10001	1	10021	10	9	10	10000	10	10000	10	458973	16	458958	0	2	458972	0	2	20012	458957	10000	14	10000	1	1	169648	42	11080	43	43	379952	117	10000	10	380022	380020	380020	380020	380020
10024	380019	2847	1	0	1	1	0	0	19998	14	1	0	0	380004	0	70267	519733	1859	518667	1067	915807	5424	10470707	0	10000	0	49	376939	0	380019	380019	138354	59939	249335	916874	1910	953894	1910	1907910	380019	380019	10001	1	10022	10	9	10	10000	10	10000	10	458973	14	458957	0	1	458972	0	1	20012	458958	10000	14	10000	1	1	169648	41	11080	42	43	379952	117	10000	10	380020	380021	380022	380050	380020
10024	380019	2847	1	1	0	1	0	0	19998	15	1	0	0	380004	0	70267	519743	1067	518667	1067	915806	5424	10470768	0	10000	0	49	376939	0	380031	380019	138355	59955	249335	916874	1910	953894	1910	1907862	380019	380019	10001	1	10021	10	9	10	10000	10	10000	10	458973	15	458958	0	0	458971	9	1	20206	458958	10000	14	10000	1	1	169652	42	11081	42	41	379953	117	10000	10	380020	380022	380020	380020	380020

STLXRB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations