Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMP (uxtw, 64-bit)

Test 1: uops

Code:

  cmp x0, w1, uxtw
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)606d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)f5f6f7f8fd
10047096082100030425200020001000408770709709498213561100010002000709781110011000073322336842000710710710710710
10047095061100030425200020001000408770709709498253561100010002000709781110011000073322336842000710710710710710
10047095061100030425200020001000408771709709498213561100010002000709781110011000073322326842000710710710710710
10047096061100030425200020001000408770709709498253561100010002000709781110011000073322336842000710710710710710
10047096061100030425200020001000408770709709498213561100010002000709781110011000073322336842000710710710710710
10047095061100030425200020001000408770709709498253561100010002000709781110011000073322336842000710710710710710
10047095061100030425200020001000408770709709498253561100010002000709781110011000073322336842000710710710710710
10047096061100030425200020001000408770709709498213561100010002000709781110011000073322336842000710710710710710
10047095061100030425200020001000408770709709498213561100010002000709781110011000073322336842000710710710710710
100470965461100030425200020001000408770709709498253561100010002000709781110011000073322336842000710710710710710

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp x0, w1, uxtw
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)031e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250611000029893253010030100201001956198149269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352240611000029893253010030100201001956198149269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352250611000029893253010030100201001956198149269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
2020430035225010401000029893253010030100201001956198149269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352250611000029893253010030100201001956198149269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
202043003522506110000298932530100301002010019561981492695530035300352736903274782010020200302003003514511202011009910020100101004600013101231222995430000101003003630036300363003630036
20204300352250611000029893253010030100201001956198149269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352250611000029893253010030100201001956198149269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352240611000029893253010030100201001956198149269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036
20204300352250611000029893253010030100201001956198149269553003530035273690327478201002020030200300351451120201100991002010010100000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
200243003522500124100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270233112995830000100103003630036300363003630036
200243003522500411100002989125300323001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270133212995830000100103003630036300363003630036
200243003522500484100002989125300103001020096195628914926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
200243003522500170100002989125300103001020010195628914926955300353003527422327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
200243003522510105100002989125300103001020010195628904923919300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
200243003522500826100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
200243003522500499100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270233112995830000100103003630036300363003630036
200243003522500451100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
200243003522500475100002989125300103001020010195628914926955300353003527391327498200102002030020300351451120021109102001010010001270133112995830000100103003630036300363003630036
200243003522500726100002989125300103001020010195628904926955300353003527391327498200102002030020300351451120021109102001010010001270133212995830000100103003630036300363003630036

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp x0, w1, uxtw
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20204300352250000000611000029893253010030100201001956198492695530035300352736932747820100202003020030035145112020110099100201001010000012032013101231222995430000101003003630036300363003630036
202043003522510120004411000029893253010030100201001956198492695530035300352736932747820100202003020030035145112020110099100201001010000013013101231222999030000101003003630036300363003630036
20204300352250000186007681000029893253010030100201001956198492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231222995430000101003003630036300363003630036
202043003522500000005361000029893253010030100201001956198492695530035300352736932747820100202003020030035145112020110099100201001010000003013101231222995430000101003003630036300363008130036
20204300352251100000611000029902253014030100201001956198492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231222995430000101003003630036300363003630036
202043003522500000001031000029893253010030100201001956198492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231222995430000101003003630036300363003630036
20204300352250000000611000029893253010030100201001956198492695530035300352736932747820100202003020030169145112020110099100201001010000033013101231222995430000101003008230036300363003630036
20204300352250000000611000029893253010030100201001956198492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231232995430000101003003630071300363003630036
20204300352250000000611000029893253010030100201001956198492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231212995430000101003003630036300363003630036
20204300352250000900611000029893253010030100201001956198492695530035300352736932747820100202003020030035145112020110099100201001010000000013101231222995430000101003003630036300363003630036

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0035

retire uop (01)cycle (02)033f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
20024300352259591000029891253001030010200101956289049269553003530035273913275292001020020300203003514511200211091020010100100001270333222995830000100103003630036300363003630036
2002430035225611000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270233222995830000100103003630036300363003630036
20024300352253821000029891253001030010200101956289049269553006630035273913274982001020020300203003514511200211091020010100100001270233222995830000100103003630036300363003630036
20024300352253771000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270233222995830000100103003630036300363003630036
20024300352255291000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270233222995830000100103003630036300363003630036
2002430035225611000029891253001030010200871956289049269553003530035273913274982001020020300203003514511200211091020010100100001270233222995830000100103003630036300363003630036
200243003522511901000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270233222995830000100103003630036300363003630036
20024300352255051000029891253001030010200101956289149269553003530035273913274982001020020300203003514511200211091020010100100001270233222995830000100103003630036300363003630036
20024300352253221000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270233222995830000100103003630036300363003630036
20024300352243621000029891253001030010200101956289049269553003530035273913274982001020020300203003514511200211091020010100100001270233222995830000100103003630036300363003630036

Test 4: throughput

Count: 8

Code:

  cmp x0, w1, uxtw
  cmp x0, w1, uxtw
  cmp x0, w1, uxtw
  cmp x0, w1, uxtw
  cmp x0, w1, uxtw
  cmp x0, w1, uxtw
  cmp x0, w1, uxtw
  cmp x0, w1, uxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6676

retire uop (01)cycle (02)03181e1f3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)696a6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
802045343440000061800004874125160100160100801003440005495033053410534104329820633433608010080200160200534107811802011009910080100100000000511032411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005495033053410534104329820633433608010080200160200534107811802011009910080100100000300511012411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005495033053410534104329820633433608010080200160200534107811802011009910080100100020000511012411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005495033053410534104329820633433608010080200160200534107811802011009910080100100000000511012411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005495033053410534104329820603433608010080200160200534107811802011009910080100100000000511012411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005495033053410534104329820603433608010080200160200534107811802011009910080100100000000511012411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005495033053410534104329820503433608010080200160200534107811802011009910080100100000000511012411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005495033053410534104329820603433608010080200160200534107811802011009910080100100000000511012411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005495033053410534104329820603433608010080200160200534107811802011009910080100100000000511012411533921600001005341153411534115341153411
802045341040000061800004874125160100160100801003440005495033053410534104329820633433608010080200160200534107811802011009910080100100000000511012411533921600001005341153411534115341153411

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6673

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e3a3f4c4d51schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)60696a6b6d6emap stall dispatch (70)flags prf full (73)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map int uop inputs (7f)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? int retires (ef)f5f6f7f8fd
80024534013990000006180000479462516001016001080010343813014950300053380533804329025623433528001080020160020533807811800211091080010100000050204245553359160000105338153381533815338153381
80024533804000001006180000479462516001016001080010343813014950300053380533804329027073433528001080020160020533807811800211091080010100000050205243353359160000105338153381533815338153381
80024533804000000006180000479462516001016001080010343813014950300053380533804329027073433528001080020160020533807811800211091080010100000050204243453359160000105338153381533815338153381
80024533804000000006180000479462516001016001080010343813014950300053380533804329025623433528001080020160020533807811800211091080010100000050203243353359160000105338153381533815338153381
80024533804000000006180000479462516001016001080010343813014950300053380533804329027073433528001080020160020533807811800211091080010100000050204243553359160000105338153381534225338153381
80024533804000000006180000479462516001016001080010343813014950300053380533804329027073433528001080020160020533807811800211091080010100000050205243353359160000105338153381533815338153381
80024533804000010006180000479462516001016001080010343813014950300053380533804329025623433528001080020160020533807811800211091080010100000050204244353359160000105338153381533815338153381
8002453380399000000111480000479462516001016001080010343813014950300053380533804329025623433528001080020160020533807811800211091080010100000050204243253359160000105338153381533815338153381
80024533803990000006180000479462516001016001080010343813014950300053380533804329025623433528001080020160020533807811800211091080010100000050204244353359160000105338153381533815338153381
80024533803990000006180000479462516001016001080010343813014950300053380533804329027073433528001080020160020533807811800211091080010100000050205243353359160000105338153381533815338153381